lkml.org 
[lkml]   [2017]   [Sep]   [18]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [V5, 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN in non-coherent DMA mode
On Mon, Sep 18, 2017 at 10:44:54AM +0100, Robin Murphy wrote:
> On 18/09/17 05:22, Huacai Chen wrote:
> > In non-coherent DMA mode, kernel uses cache flushing operations to
> > maintain I/O coherency, so the dmapool objects should be aligned to
> > ARCH_DMA_MINALIGN. Otherwise, it will cause data corruption, at least
> > on MIPS:
> >
> > Step 1, dma_map_single
> > Step 2, cache_invalidate (no writeback)
> > Step 3, dma_from_device
> > Step 4, dma_unmap_single
>
> This is a massive red warning flag for the whole series, because DMA
> pools don't work like that. At best, this will do nothing, and at worst
> it is papering over egregious bugs elsewhere. Streaming mappings of
> coherent allocations means completely broken code.

Oh, I hadn't even seen that part. Yes, dma coherent (and pool)
allocations must never be used for streaming mappings. I wish we'd
have some debug infrastructure to warn on such uses.

\
 
 \ /
  Last update: 2017-09-18 17:52    [W:0.092 / U:11.828 seconds]
©2003-2017 Jasper Spaans. hosted at Digital OceanAdvertise on this site