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SubjectRe: [PATCH v2 00/10] spi-nor: intel-spi: Various fixes and enhancements
Hi Joakim,

On Tue, Sep 12, 2017 at 1:44 AM, Joakim Tjernlund
<> wrote:
> On Mon, 2017-09-11 at 02:41 -0700, Bin Meng wrote:
>> This series does several bug fixes and clean ups against the intel-spi
>> spi-nor driver, as well as enhancements to make the driver independent
>> on the underlying BIOS/bootloader.
>> At present the driver uses the HW sequencer for the read/write/erase on
>> all supported platforms, read_reg/write_reg for BXT, and the SW sequencer
>> for read_reg/write_reg for BYT/LPT. The way the driver uses the HW and SW
>> sequencer relies on some programmed register settings and hence creates
>> unneeded dependencies with the underlying BIOS/bootloader. For example,
>> the driver unfortunately does not work as expected when booting from
>> Intel Baytrail FSP based bootloaders like U-Boot, as the Baytrail FSP
>> does not set up some SPI controller settings to make the driver happy.
>> Now such limitation has been removed with this series.
> Hi Bin
> Just starting to test these on Rangeley and got a question: We have two SPI flashes on CS0 resp. CS1
> and the mtd driver seems to only map the first of those flashes. Is this intentional or
> are we missing something?

All the boards I have tested only have one SPI flash. Mika, any comments?


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