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SubjectRe: [PATCH 03/13] openrisc: add 1 and 2 byte cmpxchg support
On Thu, Aug 31, 2017 at 09:46:54AM +0200, Peter Zijlstra wrote:
> On Thu, Aug 31, 2017 at 06:58:34AM +0900, Stafford Horne wrote:
> > OpenRISC only supports hardware instructions that perform 4 byte atomic
> > operations. For enabling qrwlocks for upcoming SMP support 1 and 2 byte
> > implementations are needed. To do this we leverage the 4 byte atomic
> > operations and shift/mask the 1 and 2 byte areas as needed.
> >
> > This heavily borrows ideas and routines from sh and mips, which do
> > something similar.
>
> Is there value in lifting them into something common?

Actually, I was planning on that as a followup patch series.

Also, the timer sync patch [13/13] could me made common which is on my todo
list.

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