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SubjectRe: [PATCH 1/2] amd: uncore: Rename cpufeatures macro for cache counters
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On 6/6/2017 11:31 AM, Borislav Petkov wrote:
> On Mon, Jun 05, 2017 at 11:13:18AM -0500, Janakarajan Natarajan wrote:
>> In Family 17h, L3 is the last level cache as opposed to L2 in previous
>> families. Avoid this name confusion and rename X86_FEATURE_PERFCT_L2 to
>> X86_FEATURE_PERFCTR_LLC to indicate the performance counter on the last
>> level of cache.
>>
>> Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com>
>> ---
>> arch/x86/events/amd/uncore.c | 2 +-
>> arch/x86/include/asm/cpufeatures.h | 2 +-
>> 2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
>> index 4d1f7f2d..8fea711 100644
>> --- a/arch/x86/events/amd/uncore.c
>> +++ b/arch/x86/events/amd/uncore.c
>> @@ -569,7 +569,7 @@ static int __init amd_uncore_init(void)
>> ret = 0;
>> }
>>
>> - if (boot_cpu_has(X86_FEATURE_PERFCTR_L2)) {
>> + if (boot_cpu_has(X86_FEATURE_PERFCTR_LLC)) {
>> amd_uncore_llc = alloc_percpu(struct amd_uncore *);
>> if (!amd_uncore_llc) {
>> ret = -ENOMEM;
>> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
>> index b04bb6d..da422d6 100644
>> --- a/arch/x86/include/asm/cpufeatures.h
>> +++ b/arch/x86/include/asm/cpufeatures.h
>> @@ -177,7 +177,7 @@
>> #define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */
>> #define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */
>> #define X86_FEATURE_PTSC ( 6*32+27) /* performance time-stamp counter */
>> -#define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */
>> +#define X86_FEATURE_PERFCTR_LLC ( 6*32+28) /* Last Level Cache performance counter extensions */
> Bah, the Zen PPR calls this PerfCtrExtL3 now. And F16h BKDG calls it
> PerfCtrExtL2I.
>
> Can this be fixed to be PerfCtrExtLLC in the docs so that there is no
> more confusion?

The PerfCtrExtL3 will be changed to PerfCtrExtLLC in the next PPR update.


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