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    SubjectRe: [PATCH v5 14/14] spi: qup: Fix QUP version identify method
    Hi Varadarajan,

    [auto build test WARNING on spi/for-next]
    [also build test WARNING on v4.13-rc2 next-20170724]
    [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

    url: https://github.com/0day-ci/linux/commits/Varadarajan-Narayanan/spi-qup-Fixes-and-add-support-for-64k-transfers/20170725-033101
    base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
    config: arm64-defconfig (attached as .config)
    compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
    reproduce:
    wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
    chmod +x ~/bin/make.cross
    # save the attached .config to linux build tree
    make.cross ARCH=arm64

    All warnings (new ones prefixed by >>):

    drivers//spi/spi-qup.c: In function 'spi_qup_probe':
    >> drivers//spi/spi-qup.c:1062:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    controller->qup_v1 = (int)of_device_get_match_data(dev);
    ^
    drivers//spi/spi-qup.c: In function 'spi_qup_transfer_one':
    drivers//spi/spi-qup.c:507:28: warning: 'tx_nents' may be used uninitialized in this function [-Wmaybe-uninitialized]
    for (; tx_sgl && tx_nents--; tx_sgl = sg_next(tx_sgl))
    ~~~~~~~~^~
    drivers//spi/spi-qup.c:464:17: note: 'tx_nents' was declared here
    u32 rx_nents, tx_nents;
    ^~~~~~~~
    drivers//spi/spi-qup.c:505:28: warning: 'rx_nents' may be used uninitialized in this function [-Wmaybe-uninitialized]
    for (; rx_sgl && rx_nents--; rx_sgl = sg_next(rx_sgl))
    ~~~~~~~~^~
    drivers//spi/spi-qup.c:464:7: note: 'rx_nents' was declared here
    u32 rx_nents, tx_nents;
    ^~~~~~~~

    vim +1062 drivers//spi/spi-qup.c

    969
    970 static int spi_qup_probe(struct platform_device *pdev)
    971 {
    972 struct spi_master *master;
    973 struct clk *iclk, *cclk;
    974 struct spi_qup *controller;
    975 struct resource *res;
    976 struct device *dev;
    977 void __iomem *base;
    978 u32 max_freq, iomode, num_cs;
    979 int ret, irq, size;
    980
    981 dev = &pdev->dev;
    982 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
    983 base = devm_ioremap_resource(dev, res);
    984 if (IS_ERR(base))
    985 return PTR_ERR(base);
    986
    987 irq = platform_get_irq(pdev, 0);
    988 if (irq < 0)
    989 return irq;
    990
    991 cclk = devm_clk_get(dev, "core");
    992 if (IS_ERR(cclk))
    993 return PTR_ERR(cclk);
    994
    995 iclk = devm_clk_get(dev, "iface");
    996 if (IS_ERR(iclk))
    997 return PTR_ERR(iclk);
    998
    999 /* This is optional parameter */
    1000 if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq))
    1001 max_freq = SPI_MAX_RATE;
    1002
    1003 if (!max_freq || max_freq > SPI_MAX_RATE) {
    1004 dev_err(dev, "invalid clock frequency %d\n", max_freq);
    1005 return -ENXIO;
    1006 }
    1007
    1008 ret = clk_prepare_enable(cclk);
    1009 if (ret) {
    1010 dev_err(dev, "cannot enable core clock\n");
    1011 return ret;
    1012 }
    1013
    1014 ret = clk_prepare_enable(iclk);
    1015 if (ret) {
    1016 clk_disable_unprepare(cclk);
    1017 dev_err(dev, "cannot enable iface clock\n");
    1018 return ret;
    1019 }
    1020
    1021 master = spi_alloc_master(dev, sizeof(struct spi_qup));
    1022 if (!master) {
    1023 clk_disable_unprepare(cclk);
    1024 clk_disable_unprepare(iclk);
    1025 dev_err(dev, "cannot allocate master\n");
    1026 return -ENOMEM;
    1027 }
    1028
    1029 /* use num-cs unless not present or out of range */
    1030 if (of_property_read_u32(dev->of_node, "num-cs", &num_cs) ||
    1031 num_cs > SPI_NUM_CHIPSELECTS)
    1032 master->num_chipselect = SPI_NUM_CHIPSELECTS;
    1033 else
    1034 master->num_chipselect = num_cs;
    1035
    1036 master->bus_num = pdev->id;
    1037 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
    1038 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
    1039 master->max_speed_hz = max_freq;
    1040 master->transfer_one = spi_qup_transfer_one;
    1041 master->dev.of_node = pdev->dev.of_node;
    1042 master->auto_runtime_pm = true;
    1043 master->dma_alignment = dma_get_cache_alignment();
    1044 master->max_dma_len = SPI_MAX_XFER;
    1045
    1046 platform_set_drvdata(pdev, master);
    1047
    1048 controller = spi_master_get_devdata(master);
    1049
    1050 controller->dev = dev;
    1051 controller->base = base;
    1052 controller->iclk = iclk;
    1053 controller->cclk = cclk;
    1054 controller->irq = irq;
    1055
    1056 ret = spi_qup_init_dma(master, res->start);
    1057 if (ret == -EPROBE_DEFER)
    1058 goto error;
    1059 else if (!ret)
    1060 master->can_dma = spi_qup_can_dma;
    1061
    > 1062 controller->qup_v1 = (int)of_device_get_match_data(dev);
    1063
    1064 if (!controller->qup_v1)
    1065 master->set_cs = spi_qup_set_cs;
    1066
    1067 spin_lock_init(&controller->lock);
    1068 init_completion(&controller->done);
    1069
    1070 iomode = readl_relaxed(base + QUP_IO_M_MODES);
    1071
    1072 size = QUP_IO_M_OUTPUT_BLOCK_SIZE(iomode);
    1073 if (size)
    1074 controller->out_blk_sz = size * 16;
    1075 else
    1076 controller->out_blk_sz = 4;
    1077
    1078 size = QUP_IO_M_INPUT_BLOCK_SIZE(iomode);
    1079 if (size)
    1080 controller->in_blk_sz = size * 16;
    1081 else
    1082 controller->in_blk_sz = 4;
    1083
    1084 size = QUP_IO_M_OUTPUT_FIFO_SIZE(iomode);
    1085 controller->out_fifo_sz = controller->out_blk_sz * (2 << size);
    1086
    1087 size = QUP_IO_M_INPUT_FIFO_SIZE(iomode);
    1088 controller->in_fifo_sz = controller->in_blk_sz * (2 << size);
    1089
    1090 dev_info(dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
    1091 controller->in_blk_sz, controller->in_fifo_sz,
    1092 controller->out_blk_sz, controller->out_fifo_sz);
    1093
    1094 writel_relaxed(1, base + QUP_SW_RESET);
    1095
    1096 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
    1097 if (ret) {
    1098 dev_err(dev, "cannot set RESET state\n");
    1099 goto error_dma;
    1100 }
    1101
    1102 writel_relaxed(0, base + QUP_OPERATIONAL);
    1103 writel_relaxed(0, base + QUP_IO_M_MODES);
    1104
    1105 if (!controller->qup_v1)
    1106 writel_relaxed(0, base + QUP_OPERATIONAL_MASK);
    1107
    1108 writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN,
    1109 base + SPI_ERROR_FLAGS_EN);
    1110
    1111 /* if earlier version of the QUP, disable INPUT_OVERRUN */
    1112 if (controller->qup_v1)
    1113 writel_relaxed(QUP_ERROR_OUTPUT_OVER_RUN |
    1114 QUP_ERROR_INPUT_UNDER_RUN | QUP_ERROR_OUTPUT_UNDER_RUN,
    1115 base + QUP_ERROR_FLAGS_EN);
    1116
    1117 writel_relaxed(0, base + SPI_CONFIG);
    1118 writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL);
    1119
    1120 ret = devm_request_irq(dev, irq, spi_qup_qup_irq,
    1121 IRQF_TRIGGER_HIGH, pdev->name, controller);
    1122 if (ret)
    1123 goto error_dma;
    1124
    1125 pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC);
    1126 pm_runtime_use_autosuspend(dev);
    1127 pm_runtime_set_active(dev);
    1128 pm_runtime_enable(dev);
    1129
    1130 ret = devm_spi_register_master(dev, master);
    1131 if (ret)
    1132 goto disable_pm;
    1133
    1134 return 0;
    1135
    1136 disable_pm:
    1137 pm_runtime_disable(&pdev->dev);
    1138 error_dma:
    1139 spi_qup_release_dma(master);
    1140 error:
    1141 clk_disable_unprepare(cclk);
    1142 clk_disable_unprepare(iclk);
    1143 spi_master_put(master);
    1144 return ret;
    1145 }
    1146

    ---
    0-DAY kernel test infrastructure Open Source Technology Center
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