Messages in this thread | | | Date | Wed, 7 Jun 2017 10:45:16 -0700 | From | Stephen Boyd <> | Subject | Re: [PATCH] clk: socfpga: Fix the smplsel on Arria10 and Stratix10 |
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On 06/07, Dinh Nguyen wrote: > The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are > offset by 1 additional bit. > > Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and > Stratix10 platforms. > > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Some sort of Fixes: tag as well?
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