lkml.org 
[lkml]   [2017]   [Jun]   [6]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    /
    Date
    From
    SubjectRe: [PATCH 2/2] amd: uncore: Get correct number of cores sharing last level cache
    On Mon, Jun 05, 2017 at 11:13:19AM -0500, Janakarajan Natarajan wrote:
    > + /*
    > + * Iterate over Cache Topology Definition leaves until no
    > + * more cache descriptions are available
    > + */
    > + while (1) {
    > + cpuid_count(0x8000001d, cache_level,
    > + &eax, &ebx, &ecx, &edx);
    > + /*
    > + * EAX[0:4] gives type of cache. 0 = No more caches
    > + */
    > + if ((eax & 0x1f) == 0)
    > + break;
    > + cache_level++;
    > + prev_eax = eax;
    > + }
    > + nshared = ((prev_eax >> 14) & 0xfff) + 1;

    Egads, could we pretty please write that in a less horrible fashion?

    Maybe something like:

    for (cache_level = 0; cache_level < 3; cache_level++) {
    cpuid_count(0x8000001d, cache_level, &eax, &ebx, &ecx, &edx);

    if ((eax & 0x1f) == 0) /* EAX[0:4] gives cache type */
    break;

    prev_eax = eax;
    }

    That way we'll not run off into the woods if CPUID goes funny (never
    trust a BIOS/virt monkey).

    \
     
     \ /
      Last update: 2017-06-12 00:43    [W:3.348 / U:0.660 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site