Messages in this thread | | | Date | Tue, 27 Jun 2017 09:48:19 +0100 | From | Will Deacon <> | Subject | Re: [PATCH 13/17] RISC-V: Add include subdirectory |
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Hi Dan,
On Tue, Jun 27, 2017 at 12:07:20AM +0000, Daniel Lustig wrote: > > > https://github.com/riscv/riscv-isa-manual/releases/download/riscv-user > > > -2.2/riscv-spec-v2.2.pdf > > > > That's the most up to date spec. > > Yes, that's the most up to date public spec. Internally, the RISC-V memory > model task group has been working on fixing the memory model spec for the > past couple of months now. We're aiming to release it for public review > well before the end of the year. Hopefully in the coming weeks even.
Excellent, cheers for the update.
> > > which, on the one hand is reassuring (because ignoring dependency > > > ordering is plain broken), but on the other it doesn't go quite far > > > enough in defining exactly what constitutes a "syntactic data > > > dependency". The cumulativity of your fences also needs defining, > > > because I think this was up in the air at some point and the document > > > above doesn't seem to tackle it (it doesn't seem to describe what > > > constitutes being a memory of the predecessor or successor sets) > > That will all covered in the new spec. > > > > P.S. You should also totally get your architects to write a formal > > > model ;) > > Also in progress :)
3/3 :)
> Were there any more specific questions I can answer in the meantime? Or > any specific concern you'd like to point me to?
Nothing specific, but we won't be able to review the memory-ordering/atomics/locking parts of this patch series until we have a spec.
Will
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