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    Subject[PATCH v4 3/6] irqchip: irq-mvebu-gicp: new driver for Marvell GICP
    Date
    This commit adds a simple driver for the Marvell GICP, a hardware unit
    that converts memory writes into GIC SPI interrupts. The driver provides
    a number of functions to the ICU driver to allocate GICP interrupts, and
    get the physical addresses that the ICUs should write to to set/clear
    interrupts.

    Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
    ---
    drivers/irqchip/Kconfig | 3 +
    drivers/irqchip/Makefile | 1 +
    drivers/irqchip/irq-mvebu-gicp.c | 279 +++++++++++++++++++++++++++++++++++++++
    drivers/irqchip/irq-mvebu-gicp.h | 12 ++
    4 files changed, 295 insertions(+)
    create mode 100644 drivers/irqchip/irq-mvebu-gicp.c
    create mode 100644 drivers/irqchip/irq-mvebu-gicp.h

    diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
    index 478f8ac..e527ee5 100644
    --- a/drivers/irqchip/Kconfig
    +++ b/drivers/irqchip/Kconfig
    @@ -268,6 +268,9 @@ config IRQ_MXS
    select IRQ_DOMAIN
    select STMP_DEVICE

    +config MVEBU_GICP
    + bool
    +
    config MVEBU_ODMI
    bool
    select GENERIC_MSI_IRQ_DOMAIN
    diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
    index b64c59b..11eb858 100644
    --- a/drivers/irqchip/Makefile
    +++ b/drivers/irqchip/Makefile
    @@ -69,6 +69,7 @@ obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o
    obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
    obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
    obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o
    +obj-$(CONFIG_MVEBU_GICP) += irq-mvebu-gicp.o
    obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
    obj-$(CONFIG_MVEBU_PIC) += irq-mvebu-pic.o
    obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
    diff --git a/drivers/irqchip/irq-mvebu-gicp.c b/drivers/irqchip/irq-mvebu-gicp.c
    new file mode 100644
    index 0000000..45358ac
    --- /dev/null
    +++ b/drivers/irqchip/irq-mvebu-gicp.c
    @@ -0,0 +1,279 @@
    +/*
    + * Copyright (C) 2017 Marvell
    + *
    + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
    + *
    + * This file is licensed under the terms of the GNU General Public
    + * License version 2. This program is licensed "as is" without any
    + * warranty of any kind, whether express or implied.
    + */
    +
    +#include <linux/io.h>
    +#include <linux/irq.h>
    +#include <linux/irqdomain.h>
    +#include <linux/msi.h>
    +#include <linux/of.h>
    +#include <linux/of_irq.h>
    +#include <linux/of_platform.h>
    +#include <linux/platform_device.h>
    +
    +#include <dt-bindings/interrupt-controller/arm-gic.h>
    +
    +#include "irq-mvebu-gicp.h"
    +
    +#define GICP_SETSPI_NSR_OFFSET 0x0
    +#define GICP_CLRSPI_NSR_OFFSET 0x8
    +
    +struct mvebu_gicp_spi_range {
    + unsigned int start;
    + unsigned int count;
    +};
    +
    +struct mvebu_gicp {
    + struct mvebu_gicp_spi_range *spi_ranges;
    + unsigned int spi_ranges_cnt;
    + unsigned int spi_cnt;
    + unsigned long *spi_bitmap;
    + spinlock_t spi_lock;
    + struct resource *res;
    + struct device *dev;
    +};
    +
    +static int gicp_idx_to_spi(struct mvebu_gicp *gicp, int idx)
    +{
    + int i;
    +
    + for (i = 0; i < gicp->spi_ranges_cnt; i++) {
    + struct mvebu_gicp_spi_range *r = &gicp->spi_ranges[i];
    +
    + if (idx < r->count)
    + return r->start + idx;
    +
    + idx -= r->count;
    + }
    +
    + return -EINVAL;
    +}
    +
    +int mvebu_gicp_get_doorbells(struct device_node *dn, phys_addr_t *setspi,
    + phys_addr_t *clrspi)
    +{
    + struct platform_device *pdev;
    + struct mvebu_gicp *gicp;
    +
    + pdev = of_find_device_by_node(dn);
    + if (!pdev)
    + return -ENODEV;
    +
    + gicp = platform_get_drvdata(pdev);
    + if (!gicp)
    + return -ENODEV;
    +
    + *setspi = gicp->res->start + GICP_SETSPI_NSR_OFFSET;
    + *clrspi = gicp->res->start + GICP_CLRSPI_NSR_OFFSET;
    +
    + return 0;
    +}
    +
    +static void gicp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
    +{
    + struct mvebu_gicp *gicp = data->chip_data;
    + phys_addr_t setspi = gicp->res->start + GICP_SETSPI_NSR_OFFSET;
    +
    + msg->data = data->hwirq;
    + msg->address_lo = lower_32_bits(setspi);
    + msg->address_hi = upper_32_bits(setspi);
    +}
    +
    +static struct irq_chip gicp_irq_chip = {
    + .name = "GICP",
    + .irq_mask = irq_chip_mask_parent,
    + .irq_unmask = irq_chip_unmask_parent,
    + .irq_eoi = irq_chip_eoi_parent,
    + .irq_set_affinity = irq_chip_set_affinity_parent,
    + .irq_set_type = irq_chip_set_type_parent,
    + .irq_compose_msi_msg = gicp_compose_msi_msg,
    +};
    +
    +static int gicp_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
    + unsigned int nr_irqs, void *args)
    +{
    + struct mvebu_gicp *gicp = domain->host_data;
    + struct irq_fwspec fwspec;
    + unsigned int hwirq;
    + int ret;
    +
    + spin_lock(&gicp->spi_lock);
    + hwirq = find_first_zero_bit(gicp->spi_bitmap, gicp->spi_cnt);
    + if (hwirq == gicp->spi_cnt) {
    + spin_unlock(&gicp->spi_lock);
    + return -ENOSPC;
    + }
    + __set_bit(hwirq, gicp->spi_bitmap);
    + spin_unlock(&gicp->spi_lock);
    +
    + fwspec.fwnode = domain->parent->fwnode;
    + fwspec.param_count = 3;
    + fwspec.param[0] = GIC_SPI;
    + fwspec.param[1] = gicp_idx_to_spi(gicp, hwirq) - 32;
    + /*
    + * Assume edge rising for now, it will be properly set when
    + * ->set_type() is called
    + */
    + fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
    +
    + ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
    + if (ret) {
    + dev_err(gicp->dev, "Cannot allocate parent IRQ\n");
    + goto free_hwirq;
    + }
    +
    + ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
    + &gicp_irq_chip, gicp);
    + if (ret)
    + goto free_irqs_parent;
    +
    + return 0;
    +
    +free_irqs_parent:
    + irq_domain_free_irqs_parent(domain, virq, nr_irqs);
    +free_hwirq:
    + spin_lock(&gicp->spi_lock);
    + __clear_bit(hwirq, gicp->spi_bitmap);
    + spin_unlock(&gicp->spi_lock);
    + return ret;
    +}
    +
    +static void gicp_irq_domain_free(struct irq_domain *domain,
    + unsigned int virq, unsigned int nr_irqs)
    +{
    + struct mvebu_gicp *gicp = domain->host_data;
    + struct irq_data *d = irq_domain_get_irq_data(domain, virq);
    +
    + if (d->hwirq >= gicp->spi_cnt) {
    + dev_err(gicp->dev, "Invalid hwirq %lu\n", d->hwirq);
    + return;
    + }
    +
    + irq_domain_free_irqs_parent(domain, virq, nr_irqs);
    +
    + spin_lock(&gicp->spi_lock);
    + __clear_bit(d->hwirq, gicp->spi_bitmap);
    + spin_unlock(&gicp->spi_lock);
    +}
    +
    +static const struct irq_domain_ops gicp_domain_ops = {
    + .alloc = gicp_irq_domain_alloc,
    + .free = gicp_irq_domain_free,
    +};
    +
    +static struct irq_chip gicp_msi_irq_chip = {
    + .name = "GICP",
    + .irq_set_type = irq_chip_set_type_parent,
    +};
    +
    +static struct msi_domain_ops gicp_msi_ops = {
    +};
    +
    +static struct msi_domain_info gicp_msi_domain_info = {
    + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
    + .ops = &gicp_msi_ops,
    + .chip = &gicp_msi_irq_chip,
    +};
    +
    +static int mvebu_gicp_probe(struct platform_device *pdev)
    +{
    + struct mvebu_gicp *gicp;
    + struct irq_domain *inner_domain, *plat_domain, *parent_domain;
    + struct device_node *node = pdev->dev.of_node;
    + struct device_node *irq_parent_dn;
    + int ret, i;
    +
    + gicp = devm_kzalloc(&pdev->dev, sizeof(*gicp), GFP_KERNEL);
    + if (!gicp)
    + return -ENOMEM;
    +
    + gicp->dev = &pdev->dev;
    +
    + gicp->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
    + if (!gicp->res)
    + return -ENODEV;
    +
    + ret = of_property_count_u32_elems(node, "marvell,spi-ranges");
    + if (ret < 0)
    + return ret;
    +
    + gicp->spi_ranges_cnt = ret / 2;
    +
    + gicp->spi_ranges =
    + devm_kzalloc(&pdev->dev,
    + gicp->spi_ranges_cnt *
    + sizeof(struct mvebu_gicp_spi_range),
    + GFP_KERNEL);
    + if (!gicp->spi_ranges)
    + return -ENOMEM;
    +
    + for (i = 0; i < gicp->spi_ranges_cnt; i++) {
    + of_property_read_u32_index(node, "marvell,spi-ranges",
    + i * 2,
    + &gicp->spi_ranges[i].start);
    +
    + of_property_read_u32_index(node, "marvell,spi-ranges",
    + i * 2 + 1,
    + &gicp->spi_ranges[i].count);
    +
    + gicp->spi_cnt += gicp->spi_ranges[i].count;
    + }
    +
    + gicp->spi_bitmap = devm_kzalloc(&pdev->dev,
    + BITS_TO_LONGS(gicp->spi_cnt),
    + GFP_KERNEL);
    + if (!gicp->spi_bitmap)
    + return -ENOMEM;
    +
    + irq_parent_dn = of_irq_find_parent(node);
    + if (!irq_parent_dn) {
    + dev_err(&pdev->dev, "failed to find parent IRQ node\n");
    + return -ENODEV;
    + }
    +
    + parent_domain = irq_find_host(irq_parent_dn);
    + if (!parent_domain) {
    + dev_err(&pdev->dev, "failed to find parent IRQ domain\n");
    + return -ENODEV;
    + }
    +
    + inner_domain = irq_domain_create_hierarchy(parent_domain, 0,
    + gicp->spi_cnt,
    + of_node_to_fwnode(node),
    + &gicp_domain_ops, gicp);
    + if (!inner_domain)
    + return -ENOMEM;
    +
    +
    + plat_domain = platform_msi_create_irq_domain(of_node_to_fwnode(node),
    + &gicp_msi_domain_info,
    + inner_domain);
    + if (!plat_domain) {
    + irq_domain_remove(inner_domain);
    + return -ENOMEM;
    + }
    +
    + platform_set_drvdata(pdev, gicp);
    +
    + return 0;
    +}
    +
    +static const struct of_device_id mvebu_gicp_of_match[] = {
    + { .compatible = "marvell,ap806-gicp", },
    + {},
    +};
    +
    +static struct platform_driver mvebu_gicp_driver = {
    + .probe = mvebu_gicp_probe,
    + .driver = {
    + .name = "mvebu-gicp",
    + .of_match_table = mvebu_gicp_of_match,
    + },
    +};
    +builtin_platform_driver(mvebu_gicp_driver);
    diff --git a/drivers/irqchip/irq-mvebu-gicp.h b/drivers/irqchip/irq-mvebu-gicp.h
    new file mode 100644
    index 0000000..89a8dc2
    --- /dev/null
    +++ b/drivers/irqchip/irq-mvebu-gicp.h
    @@ -0,0 +1,12 @@
    +#ifndef __MVEBU_GICP_H__
    +#define __MVEBU_GICP_H__
    +
    +#include <linux/types.h>
    +
    +struct device_node;
    +
    +int mvebu_gicp_get_doorbells(struct device_node *dn, phys_addr_t *setspi,
    + phys_addr_t *clrspi);
    +
    +#endif /* __MVEBU_GICP_H__ */
    +
    --
    2.9.4
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      Last update: 2017-06-20 16:09    [W:2.415 / U:0.184 seconds]
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