Messages in this thread | | | Date | Mon, 19 Jun 2017 18:01:25 -0700 | From | Stephen Boyd <> | Subject | Re: [PATCH v6 1/3] clk: imx7d: create clocks behind rawnand clock gate |
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On 06/08, Stefan Agner wrote: > The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT > and NAND_CLK_ROOT. However, the gate has been in the chain of the > latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT > only, e.g. as required by APBH-Bridge-DMA. > > Add new clocks which represent the clock after the gate, and use a > shared clock gate to correctly model the hardware. > > Signed-off-by: Stefan Agner <stefan@agner.ch> > Tested-by: Fabio Estevam <fabio.estevam@nxp.com> > ---
Applied to clk-next
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