Messages in this thread | | | Subject | Re: [PATCH v2 00/10] PCID and improved laziness | From | Dave Hansen <> | Date | Wed, 14 Jun 2017 15:18:26 -0700 |
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On 06/13/2017 09:56 PM, Andy Lutomirski wrote: > 2. Mms that have been used recently on a given CPU might get to keep > their TLB entries alive across process switches with this patch > set. TLB fills are pretty fast on modern CPUs, but they're even > faster when they don't happen.
Let's not forget that TLBs are also getting bigger. The bigger TLBs help ensure that they *can* survive across another process's timeslice.
Also, the cost to refill the paging structure caches is going up. Just think of how many cachelines you have to pull in to populate a ~1500-entry TLB, even if the CPU hid the latency of those loads.
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