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    Subject[PATCH 4.9 047/164] drm/amdgpu: Make display watermark calculations more accurate
    Date
    4.9-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Mario Kleiner <mario.kleiner.de@gmail.com>

    commit d63c277dc672e0c568481af043359420fa9d4736 upstream.

    Avoid big roundoff errors in scanline/hactive durations for
    high pixel clocks, especially for >= 500 Mhz, and thereby
    program more accurate display fifo watermarks.

    Implemented here for DCE 6,8,10,11.
    Successfully tested on DCE 10 with AMD R9 380 Tonga.

    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 10 +++++-----
    drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 10 +++++-----
    drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 10 +++++-----
    drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 10 +++++-----
    4 files changed, 20 insertions(+), 20 deletions(-)

    --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
    +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
    @@ -1297,14 +1297,14 @@ static void dce_v10_0_program_watermarks
    {
    struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
    struct dce10_wm_params wm_low, wm_high;
    - u32 pixel_period;
    + u32 active_time;
    u32 line_time = 0;
    u32 latency_watermark_a = 0, latency_watermark_b = 0;
    u32 tmp, wm_mask, lb_vblank_lead_lines = 0;

    if (amdgpu_crtc->base.enabled && num_heads && mode) {
    - pixel_period = 1000000 / (u32)mode->clock;
    - line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
    + active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
    + line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);

    /* watermark for high clocks */
    if (adev->pm.dpm_enabled) {
    @@ -1319,7 +1319,7 @@ static void dce_v10_0_program_watermarks

    wm_high.disp_clk = mode->clock;
    wm_high.src_width = mode->crtc_hdisplay;
    - wm_high.active_time = mode->crtc_hdisplay * pixel_period;
    + wm_high.active_time = active_time;
    wm_high.blank_time = line_time - wm_high.active_time;
    wm_high.interlaced = false;
    if (mode->flags & DRM_MODE_FLAG_INTERLACE)
    @@ -1358,7 +1358,7 @@ static void dce_v10_0_program_watermarks

    wm_low.disp_clk = mode->clock;
    wm_low.src_width = mode->crtc_hdisplay;
    - wm_low.active_time = mode->crtc_hdisplay * pixel_period;
    + wm_low.active_time = active_time;
    wm_low.blank_time = line_time - wm_low.active_time;
    wm_low.interlaced = false;
    if (mode->flags & DRM_MODE_FLAG_INTERLACE)
    --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
    +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
    @@ -1264,14 +1264,14 @@ static void dce_v11_0_program_watermarks
    {
    struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
    struct dce10_wm_params wm_low, wm_high;
    - u32 pixel_period;
    + u32 active_time;
    u32 line_time = 0;
    u32 latency_watermark_a = 0, latency_watermark_b = 0;
    u32 tmp, wm_mask, lb_vblank_lead_lines = 0;

    if (amdgpu_crtc->base.enabled && num_heads && mode) {
    - pixel_period = 1000000 / (u32)mode->clock;
    - line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
    + active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
    + line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);

    /* watermark for high clocks */
    if (adev->pm.dpm_enabled) {
    @@ -1286,7 +1286,7 @@ static void dce_v11_0_program_watermarks

    wm_high.disp_clk = mode->clock;
    wm_high.src_width = mode->crtc_hdisplay;
    - wm_high.active_time = mode->crtc_hdisplay * pixel_period;
    + wm_high.active_time = active_time;
    wm_high.blank_time = line_time - wm_high.active_time;
    wm_high.interlaced = false;
    if (mode->flags & DRM_MODE_FLAG_INTERLACE)
    @@ -1325,7 +1325,7 @@ static void dce_v11_0_program_watermarks

    wm_low.disp_clk = mode->clock;
    wm_low.src_width = mode->crtc_hdisplay;
    - wm_low.active_time = mode->crtc_hdisplay * pixel_period;
    + wm_low.active_time = active_time;
    wm_low.blank_time = line_time - wm_low.active_time;
    wm_low.interlaced = false;
    if (mode->flags & DRM_MODE_FLAG_INTERLACE)
    --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
    +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
    @@ -1057,7 +1057,7 @@ static void dce_v6_0_program_watermarks(
    struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
    struct dce6_wm_params wm_low, wm_high;
    u32 dram_channels;
    - u32 pixel_period;
    + u32 active_time;
    u32 line_time = 0;
    u32 latency_watermark_a = 0, latency_watermark_b = 0;
    u32 priority_a_mark = 0, priority_b_mark = 0;
    @@ -1067,8 +1067,8 @@ static void dce_v6_0_program_watermarks(
    fixed20_12 a, b, c;

    if (amdgpu_crtc->base.enabled && num_heads && mode) {
    - pixel_period = 1000000 / (u32)mode->clock;
    - line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
    + active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
    + line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
    priority_a_cnt = 0;
    priority_b_cnt = 0;

    @@ -1087,7 +1087,7 @@ static void dce_v6_0_program_watermarks(

    wm_high.disp_clk = mode->clock;
    wm_high.src_width = mode->crtc_hdisplay;
    - wm_high.active_time = mode->crtc_hdisplay * pixel_period;
    + wm_high.active_time = active_time;
    wm_high.blank_time = line_time - wm_high.active_time;
    wm_high.interlaced = false;
    if (mode->flags & DRM_MODE_FLAG_INTERLACE)
    @@ -1114,7 +1114,7 @@ static void dce_v6_0_program_watermarks(

    wm_low.disp_clk = mode->clock;
    wm_low.src_width = mode->crtc_hdisplay;
    - wm_low.active_time = mode->crtc_hdisplay * pixel_period;
    + wm_low.active_time = active_time;
    wm_low.blank_time = line_time - wm_low.active_time;
    wm_low.interlaced = false;
    if (mode->flags & DRM_MODE_FLAG_INTERLACE)
    --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
    +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
    @@ -1218,14 +1218,14 @@ static void dce_v8_0_program_watermarks(
    {
    struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
    struct dce8_wm_params wm_low, wm_high;
    - u32 pixel_period;
    + u32 active_time;
    u32 line_time = 0;
    u32 latency_watermark_a = 0, latency_watermark_b = 0;
    u32 tmp, wm_mask, lb_vblank_lead_lines = 0;

    if (amdgpu_crtc->base.enabled && num_heads && mode) {
    - pixel_period = 1000000 / (u32)mode->clock;
    - line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
    + active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
    + line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);

    /* watermark for high clocks */
    if (adev->pm.dpm_enabled) {
    @@ -1240,7 +1240,7 @@ static void dce_v8_0_program_watermarks(

    wm_high.disp_clk = mode->clock;
    wm_high.src_width = mode->crtc_hdisplay;
    - wm_high.active_time = mode->crtc_hdisplay * pixel_period;
    + wm_high.active_time = active_time;
    wm_high.blank_time = line_time - wm_high.active_time;
    wm_high.interlaced = false;
    if (mode->flags & DRM_MODE_FLAG_INTERLACE)
    @@ -1279,7 +1279,7 @@ static void dce_v8_0_program_watermarks(

    wm_low.disp_clk = mode->clock;
    wm_low.src_width = mode->crtc_hdisplay;
    - wm_low.active_time = mode->crtc_hdisplay * pixel_period;
    + wm_low.active_time = active_time;
    wm_low.blank_time = line_time - wm_low.active_time;
    wm_low.interlaced = false;
    if (mode->flags & DRM_MODE_FLAG_INTERLACE)

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