lkml.org 
[lkml]   [2017]   [May]   [1]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    /
    From
    Date
    SubjectRe: powerpc/8xx: Adding support of IRQ in MPC8xx GPIO
    On Mon, 2017-05-01 at 09:46 +0200, christophe leroy wrote:
    >
    > Le 30/04/2017 à 08:48, Scott Wood a écrit :
    > > On Thu, Mar 09, 2017 at 10:42:04AM +0100, Christophe Leroy wrote:
    > > >
    > > > @@ -625,6 +641,14 @@ int cpm1_gpiochip_add16(struct device_node *np)
    > > >
    > > >   spin_lock_init(&cpm1_gc->lock);
    > > >
    > > > + if (!of_property_read_u16(np, "interrupts-mask", &mask)) {
    > > > + int i, j;
    > > > +
    > > > + for (i = 0, j = 0; i < 16; i++)
    > > > + if (mask & (1 << (15 - i)))
    > > > + cpm1_gc->irq[i] =
    > > > irq_of_parse_and_map(np, j++);
    > > > + }
    > >
    > > Do we really need to use MSB-first bit numbering here?
    >
    > Well, I think it is better to keep the GPIOs in the same order as in the 
    > CPM1 registers, like everywhere else in that driver, isn't it ?
    >
    > The registers have GPIO 0 in the MSB and GPIO15 in the LSB.

    OK, if there's a specific register this is reflecting that's reasonable.

    -Scott

    \
     
     \ /
      Last update: 2017-05-01 20:15    [W:5.657 / U:0.228 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site