Messages in this thread Patch in this message | | | From | Piotr Luc <> | Subject | [PATCH v1] x86/mce: enable PPIN for Knights Landing/Mill | Date | Sat, 8 Apr 2017 19:20:04 +0200 |
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Intel Xeon Phi processors (KNL and KNM) do support PPIN as well, so we add their CPUIDs to the whitelist of supported processors. PPIN is a unique number that allows to determine origin of the CPU, from now on will be logged when an mce error occur.
Signed-off-by: Piotr Luc <piotr.luc@intel.com> --- arch/x86/kernel/cpu/mcheck/mce_intel.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c index 190b3e6..f1c44c3 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_intel.c +++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c @@ -481,6 +481,8 @@ static void intel_ppin_init(struct cpuinfo_x86 *c) case INTEL_FAM6_BROADWELL_XEON_D: case INTEL_FAM6_BROADWELL_X: case INTEL_FAM6_SKYLAKE_X: + case INTEL_FAM6_XEON_PHI_KNL: + case INTEL_FAM6_XEON_PHI_KNM: if (rdmsrl_safe(MSR_PPIN_CTL, &val)) return; -- 2.10.1
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