lkml.org 
[lkml]   [2017]   [Apr]   [27]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
Subject[PATCH 0/3] Cavium ThunderX2 SMMUv3 errata workarounds
Date
From: Geetha <gakula@cavium.com>

Cavium CN99xx SMMUv3 implementation has two Silicon Erratas.
1. Errata ID #74
SMMU register alias Page 1 is not implemented
2. Errata ID #126
SMMU doesnt support unique IRQ lines for gerror, eventq and cmdq-sync

The following patchset does software workaround for these two erratas.

This series is based on RFC patch.
https://www.spinics.net/lists/arm-kernel/msg575739.html

As suggested by Will Deacon, code is modified to use silicon id to
enable errata#74 workaround.

Linu Cherian (1):
iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

Geetha (2):
arm64: Add MIDR values for Cavium cn99xx SoCs
iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126

Documentation/arm64/silicon-errata.txt | 2 ++
arch/arm64/include/asm/cputype.h | 3 ++
drivers/acpi/arm64/iort.c | 14 +++++++-
drivers/iommu/arm-smmu-v3.c | 64 +++++++++++++++++++++++++++++-----
4 files changed, 73 insertions(+), 10 deletions(-)

--
1.9.1

\
 
 \ /
  Last update: 2017-04-27 14:06    [W:0.070 / U:1.124 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site