Messages in this thread | | | Date | Fri, 21 Apr 2017 19:38:48 -0700 | From | Stephen Boyd <> | Subject | Re: [PATCH] clk: tegra: fix SS control on PLL enable/disable |
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On 04/20, Peter De Schrijver wrote: > PLL SS was only controlled when setting the PLL rate, not when the PLL > itself is enabled or disabled. This means that if the PLL rate was set > before the PLL is enabled, SS will not be enabled, even when configured. > > Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Fixes tag? Or this isn't a problem right now, just future fix?
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