[lkml]   [2017]   [Apr]   [21]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
SubjectRe: [PATCH] clk: tegra: fix SS control on PLL enable/disable
On 04/20, Peter De Schrijver wrote:
> PLL SS was only controlled when setting the PLL rate, not when the PLL
> itself is enabled or disabled. This means that if the PLL rate was set
> before the PLL is enabled, SS will not be enabled, even when configured.
> Signed-off-by: Peter De Schrijver <>

Fixes tag? Or this isn't a problem right now, just future fix?

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

 \ /
  Last update: 2017-04-22 04:39    [W:0.107 / U:0.560 seconds]
©2003-2018 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site