Messages in this thread Patch in this message | | | From | Borislav Petkov <> | Subject | [PATCH] x86/mce: Enable PPIN for Knights Landing/Mill | Date | Thu, 13 Apr 2017 22:10:56 +0200 |
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From: Piotr Luc <piotr.luc@intel.com>
Intel Xeon Phi processors (KNL and KNM) do support PPIN as well, so add their CPUIDs to the whitelist of supported processors.
Signed-off-by: Piotr Luc <piotr.luc@intel.com> Cc: Tony Luck <tony.luck@intel.com> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: x86-ml <x86@kernel.org> Link: http://lkml.kernel.org/r/20170408172004.8463-1-piotr.luc@intel.com Signed-off-by: Borislav Petkov <bp@suse.de> --- arch/x86/kernel/cpu/mcheck/mce_intel.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c index 190b3e6cef4d..e84db79ef272 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_intel.c +++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c @@ -481,6 +481,9 @@ static void intel_ppin_init(struct cpuinfo_x86 *c) case INTEL_FAM6_BROADWELL_XEON_D: case INTEL_FAM6_BROADWELL_X: case INTEL_FAM6_SKYLAKE_X: + case INTEL_FAM6_XEON_PHI_KNL: + case INTEL_FAM6_XEON_PHI_KNM: + if (rdmsrl_safe(MSR_PPIN_CTL, &val)) return; -- 2.11.0
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