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SubjectRe: [PATCH v12 4/9] mmc: cavium: Work-around hardware bug on cn6xxx and cnf7xxx
On Fri, Mar 17, 2017 at 3:13 PM, Ulf Hansson <ulf.hansson@linaro.org> wrote:
> On 10 March 2017 at 14:25, Jan Glauber <jglauber@cavium.com> wrote:
>> Prevent data corruption on cn6xxx and cnf7xxx.
>> Due to an imperfection in the design of the MMC bus hardware,
>> + */
>> +void l2c_unlock_mem_region(u64 start, u64 len)
>> +{
>> + u64 end;
>> +
>> + /* Round start/end to cache line boundaries */
>> + end = ALIGN(start + len - 1, CVMX_CACHE_LINE_SIZE);
>> + start = ALIGN(start, CVMX_CACHE_LINE_SIZE);
>> +
>> + while (start <= end) {
>> + l2c_unlock_line(start);
>> + start += CVMX_CACHE_LINE_SIZE;
>> + }
>> +}
>> +EXPORT_SYMBOL_GPL(l2c_unlock_mem_region);
>
> It seems like we should be able to implement these functions in the
> octeon mmc driver, instead of having to export some SoC specific APIs.
> You only need to figure out how to find the correct CACHE_LINE_SIZE,
> but that should be possible to fix.
>
> My point is really that we should avoid exporting SoC specific APIs
> which shall be called from drivers. This is old fashion.

Right, we wouldn't do this on arm64 either, so it's better not to introduce
it for mips now when you want to have an arm64 version next.
You should also try to have every driver enabled for
CONFIG_COMPILE_TEST, which doesn't work with architecture
specific hacks.

Arnd

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