Messages in this thread | | | Date | Mon, 20 Feb 2017 12:00:09 +0100 | From | Peter Zijlstra <> | Subject | Re: [PATCH v3] locking/pvqspinlock: Relax cmpxchg's to improve performance on some archs |
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On Mon, Feb 20, 2017 at 05:20:52AM +0100, Andrea Parri wrote: > On Fri, Feb 17, 2017 at 03:43:40PM -0500, Waiman Long wrote:
> > @@ -361,6 +361,9 @@ static void pv_kick_node(struct qspinlock *lock, struct mcs_spinlock *node) > > * observe its next->locked value and advance itself. > > * > > * Matches with smp_store_mb() and cmpxchg() in pv_wait_node() > > + * > > + * We can't used relaxed form of cmpxchg here as the loading of > > + * pn->state can happen before setting next->locked in some archs. > > */ > > if (cmpxchg(&pn->state, vcpu_halted, vcpu_hashed) != vcpu_halted) > > Hi Waiman. > > cmpxchg() does not guarantee the (here implied) smp_mb(), in general; c.f., > e.g., arch/arm64/include/asm/atomic_ll_sc.h, where cmpxchg() get "compiled" > to something like: > > _loop: ldxr; eor; cbnz _exit; stlxr; cbnz _loop; dmb ish; _exit:
So cmpxchg() should have an effective smp_mb() before and after the operation, _except_ in the case of failure, in which case it need not imply any barrier.
And since a successful cmpxchg does the store, which is a store-release in that arm64 sequence, that provides the ordering against all prior state. The dmb-ish provides the required barrier after the operation.
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