Messages in this thread | | | Date | Mon, 13 Feb 2017 12:28:49 -0800 | From | "Paul E. McKenney" <> | Subject | Re: Question about DEC Alpha memory ordering |
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On Mon, Feb 13, 2017 at 08:14:23PM +0100, Tobias Klausmann wrote: > Hi! > > On Mon, 13 Feb 2017, Paul E. McKenney wrote: > > On Mon, Feb 13, 2017 at 01:53:27PM -0500, bob smith wrote: > > > On 2/13/17 1:39 PM, Paul E. McKenney wrote: > > > > can real DEC Alpha hardware end up with both instances of "r1" > > > > having the value 1? > > > > > > I thought this question reminded me of something, so I found this: > > > > https://www.kernel.org/doc/Documentation/memory-barriers.txt > > > > > > and I pasted in the content - David Howells is one of the authors and > > > maybe that is why the question sort of reminded me. > > > > > > Maybe someone has an update but this is what was said then. > > > > Well, thank you for pointing me to this, but my question was intended to > > check whether or not the words I helped to write in memory-barriers.txt > > are in fact accurate. So if you have an SMP DEC Alpha system that you > > could provide remote access to, that would be very helpful! > > I have a 4-cpu ES40. Send me a test program and I'll gladly run > it for you.
Andrea, could you please convert the litmus test below and send it to Tobias?
Thanx, Paul
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C auto/C-LB-LRW+OB-Dv (* * Result: Never * *) { }
P0(int *u0, int *x1) { r1 = READ_ONCE(*u0); smp_mb(); WRITE_ONCE(*x1, 1); }
P1(int *u0, int *x1) { r1 = rcu_dereference(*x1); WRITE_ONCE(*u0, r1); }
exists (0:r1=1 /\ 1:r1=1)
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