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SubjectRe: [PATCH v4 6/9] drm/i915: Make use of indexed write GMBUS feature
On Wed, Dec 06, 2017 at 07:00:09PM -0500, Sean Paul wrote:
> This patch enables the indexed write feature of the GMBUS to concatenate
> 2 consecutive messages into one. The criteria for an indexed write is
> that both messages are writes, the first is length == 1, and the second
> is length > 0. The first message is sent out by the GMBUS as the slave
> command, and the second one is sent via the GMBUS FIFO as usual.
>
> Changes in v3:
> - Added to series
> Changes in v4:
> - Combine indexed reads and writes (Ville)
>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Sean Paul <seanpaul@chromium.org>

Even prettier!

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

> ---
> drivers/gpu/drm/i915/intel_i2c.c | 34 ++++++++++++++++++++--------------
> 1 file changed, 20 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index 49fdf09f9919..d78ce758fbfa 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -373,7 +373,8 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
>
> static int
> gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
> - unsigned short addr, u8 *buf, unsigned int len)
> + unsigned short addr, u8 *buf, unsigned int len,
> + u32 gmbus1_index)
> {
> unsigned int chunk_size = len;
> u32 val, loop;
> @@ -386,7 +387,7 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
>
> I915_WRITE_FW(GMBUS3, val);
> I915_WRITE_FW(GMBUS1,
> - GMBUS_CYCLE_WAIT |
> + gmbus1_index | GMBUS_CYCLE_WAIT |
> (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
> (addr << GMBUS_SLAVE_ADDR_SHIFT) |
> GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
> @@ -409,7 +410,8 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
> }
>
> static int
> -gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
> +gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
> + u32 gmbus1_index)
> {
> u8 *buf = msg->buf;
> unsigned int tx_size = msg->len;
> @@ -419,7 +421,8 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
> do {
> len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
>
> - ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len);
> + ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
> + gmbus1_index);
> if (ret)
> return ret;
>
> @@ -431,21 +434,21 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
> }
>
> /*
> - * The gmbus controller can combine a 1 or 2 byte write with a read that
> - * immediately follows it by using an "INDEX" cycle.
> + * The gmbus controller can combine a 1 or 2 byte write with another read/write
> + * that immediately follows it by using an "INDEX" cycle.
> */
> static bool
> -gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
> +gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
> {
> return (i + 1 < num &&
> msgs[i].addr == msgs[i + 1].addr &&
> !(msgs[i].flags & I2C_M_RD) &&
> (msgs[i].len == 1 || msgs[i].len == 2) &&
> - (msgs[i + 1].flags & I2C_M_RD));
> + msgs[i + 1].len > 0);
> }
>
> static int
> -gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
> +gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
> {
> u32 gmbus1_index = 0;
> u32 gmbus5 = 0;
> @@ -462,7 +465,10 @@ gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
> if (gmbus5)
> I915_WRITE_FW(GMBUS5, gmbus5);
>
> - ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
> + if (msgs[1].flags & I2C_M_RD)
> + ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
> + else
> + ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index);
>
> /* Clear GMBUS5 after each index transfer */
> if (gmbus5)
> @@ -486,13 +492,13 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
>
> for (; i < num; i += inc) {
> inc = 1;
> - if (gmbus_is_index_read(msgs, i, num)) {
> - ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
> - inc = 2; /* an index read is two msgs */
> + if (gmbus_is_index_xfer(msgs, i, num)) {
> + ret = gmbus_index_xfer(dev_priv, &msgs[i]);
> + inc = 2; /* an index transmission is two msgs */
> } else if (msgs[i].flags & I2C_M_RD) {
> ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
> } else {
> - ret = gmbus_xfer_write(dev_priv, &msgs[i]);
> + ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);
> }
>
> if (!ret)
> --
> 2.15.1.424.g9478a66081-goog
>

--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch

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