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    Subject[PATCH AUTOSEL for 4.14 048/135] clk: tegra: Fix cclk_lp divisor register
    Date
    From: Michał Mirosław <mirq-linux@rere.qmqm.pl>

    [ Upstream commit 54eff2264d3e9fd7e3987de1d7eba1d3581c631e ]

    According to comments in code and common sense, cclk_lp uses its
    own divisor, not cclk_g's.

    Fixes: b08e8c0ecc42 ("clk: tegra: add clock support for Tegra30")
    Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
    Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
    Signed-off-by: Thierry Reding <treding@nvidia.com>
    Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
    ---
    drivers/clk/tegra/clk-tegra30.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
    index a2d163f759b4..07f5203df01c 100644
    --- a/drivers/clk/tegra/clk-tegra30.c
    +++ b/drivers/clk/tegra/clk-tegra30.c
    @@ -964,7 +964,7 @@ static void __init tegra30_super_clk_init(void)
    * U71 divider of cclk_lp.
    */
    clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
    - clk_base + SUPER_CCLKG_DIVIDER, 0,
    + clk_base + SUPER_CCLKLP_DIVIDER, 0,
    TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
    clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);

    --
    2.11.0
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