Messages in this thread Patch in this message | | | From | Bryan O'Donoghue <> | Subject | [PATCH 25/33] clk: tegra: pll: change clk_pll_round_rate() return logic | Date | Sat, 30 Dec 2017 01:13:04 +0000 |
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This patch updates the round_rate() logic here to return zero instead of a negative number on error.
In conjunction with higher-level changes associated with acting on the return value of clk_ops->round_rate() it is then possible to have clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of the current limitation of 1 Hz to LONG_MAX Hz.
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: linux-clk@vger.kernel.org Cc: linux-tegra@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Rhyland Klein <rklein@nvidia.com> Cc: Bill Huang <bilhuang@nvidia.com> --- drivers/clk/tegra/clk-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index b4a7d30..0a3edb0 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -839,7 +839,7 @@ static unsigned long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, if (_get_table_rate(hw, &cfg, rate, *prate) && pll->params->calc_rate(hw, &cfg, rate, *prate)) - return -EINVAL; + return 0; return cfg.output_rate; } -- 2.7.4
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