lkml.org 
[lkml]   [2017]   [Dec]   [20]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    /
    From
    Subject[PATCH 0/4] Add support for Intel IOMMU 5-level paging
    Date
    Hi All,

    Upcoming hardware plans to introduce support for 5-level paging[1]. The support
    for CPU 5-level paging has already been merged in kernel v4.14. The following
    patches add support for Intel IOMMU 5-level paging. The patches are based on
    the Intel Virtualization Technology for Directed I/O spec revision - 2.5 [2]

    Intel IOMMU Extended-context entries support two levels of translation,
    referred to as first-level translation and second-level translation. The first
    level page table points to CPU page table when IOMMU is using Shared virtual
    memory(SVM). The second level page tables are built by IOMMU driver for IOVA
    translations when functions like dma_map/iommu_map are called.

    Use of 5-level paging for first-level translation is controlled through
    programming of the new paging mode field in the PASID entry for the IOMMU PASID
    (Process Address space ID) table. Use of 5-level paging for second-level
    translation is controlled through the programming of already existing Address
    Width (AW) field in the context/extended-context entry.

    The first patch adds 5-level paging support for second level translations by
    increasing the supported domain address width. The following patches add the
    necessary checks before enabling SVM. The last patch programs the 5-level
    paging mode in the PASID entry.

    Regards,
    Sohil

    [1] https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf
    [2] https://software.intel.com/sites/default/files/managed/c5/15/vt-directed-io-spec.pdf


    Sohil Mehta (4):
    iommu/vt-d: Enable upto 57 bits of domain address width
    iommu/vt-d: Add a check for 1GB page support
    iommu/vt-d: Add a check for 5-level paging support
    iommu/vt-d: Enable 5-level paging mode in the PASID entry

    drivers/iommu/intel-iommu.c | 2 +-
    drivers/iommu/intel-svm.c | 23 +++++++++++++++++++++--
    include/linux/intel-iommu.h | 2 ++
    3 files changed, 24 insertions(+), 3 deletions(-)

    --
    2.7.4

    \
     
     \ /
      Last update: 2017-12-20 20:59    [W:3.955 / U:0.020 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site