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    Subject[PATCH v2 09/11] clk: qcom: ipq8074: add GP and Crypto clocks
    Date
    - It has 3 general purpose clock controller which supplies
    the clock in GPIO pins.
    - It has Crypto Engine which has AXI, AHB and Core clocks.
    Other non APSS processors can also use Crypto Engine so
    these clocks are marked as VOTED clocks.

    Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
    ---
    drivers/clk/qcom/gcc-ipq8074.c | 199 +++++++++++++++++++++++++++++++++++++++++
    1 file changed, 199 insertions(+)

    diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
    index be919bb..3aad6bc 100644
    --- a/drivers/clk/qcom/gcc-ipq8074.c
    +++ b/drivers/clk/qcom/gcc-ipq8074.c
    @@ -390,6 +390,22 @@ enum {
    { P_BIAS_PLL, 6 },
    };

    +static const char * const gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
    + "xo",
    + "gpll0",
    + "gpll6",
    + "gpll0_out_main_div2",
    + "sleep_clk",
    +};
    +
    +static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
    + { P_XO, 0 },
    + { P_GPLL0, 1 },
    + { P_GPLL6, 2 },
    + { P_GPLL0_DIV2, 4 },
    + { P_SLEEP_CLK, 6 },
    +};
    +
    static struct clk_alpha_pll gpll0_main = {
    .offset = 0x21000,
    .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
    @@ -1939,6 +1955,74 @@ enum {
    },
    };

    +static struct freq_tbl ftbl_crypto_clk_src[] = {
    + F(40000000, P_GPLL0_DIV2, 10, 0, 0),
    + F(80000000, P_GPLL0, 10, 0, 0),
    + F(100000000, P_GPLL0, 8, 0, 0),
    + F(160000000, P_GPLL0, 5, 0, 0),
    + { }
    +};
    +
    +static struct clk_rcg2 crypto_clk_src = {
    + .cmd_rcgr = 0x16004,
    + .freq_tbl = ftbl_crypto_clk_src,
    + .hid_width = 5,
    + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
    + .clkr.hw.init = &(struct clk_init_data){
    + .name = "crypto_clk_src",
    + .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
    + .num_parents = 3,
    + .ops = &clk_rcg2_ops,
    + },
    +};
    +
    +static struct freq_tbl ftbl_gp_clk_src[] = {
    + F(19200000, P_XO, 1, 0, 0),
    + { }
    +};
    +
    +static struct clk_rcg2 gp1_clk_src = {
    + .cmd_rcgr = 0x08004,
    + .freq_tbl = ftbl_gp_clk_src,
    + .mnd_width = 8,
    + .hid_width = 5,
    + .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
    + .clkr.hw.init = &(struct clk_init_data){
    + .name = "gp1_clk_src",
    + .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
    + .num_parents = 5,
    + .ops = &clk_rcg2_ops,
    + },
    +};
    +
    +static struct clk_rcg2 gp2_clk_src = {
    + .cmd_rcgr = 0x09004,
    + .freq_tbl = ftbl_gp_clk_src,
    + .mnd_width = 8,
    + .hid_width = 5,
    + .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
    + .clkr.hw.init = &(struct clk_init_data){
    + .name = "gp2_clk_src",
    + .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
    + .num_parents = 5,
    + .ops = &clk_rcg2_ops,
    + },
    +};
    +
    +static struct clk_rcg2 gp3_clk_src = {
    + .cmd_rcgr = 0x0a004,
    + .freq_tbl = ftbl_gp_clk_src,
    + .mnd_width = 8,
    + .hid_width = 5,
    + .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
    + .clkr.hw.init = &(struct clk_init_data){
    + .name = "gp3_clk_src",
    + .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
    + .num_parents = 5,
    + .ops = &clk_rcg2_ops,
    + },
    +};
    +
    static struct clk_branch gcc_blsp1_ahb_clk = {
    .halt_reg = 0x01008,
    .clkr = {
    @@ -4137,6 +4221,111 @@ enum {
    },
    };

    +static struct clk_branch gcc_crypto_ahb_clk = {
    + .halt_reg = 0x16024,
    + .halt_check = BRANCH_HALT_VOTED,
    + .clkr = {
    + .enable_reg = 0x0b004,
    + .enable_mask = BIT(0),
    + .hw.init = &(struct clk_init_data){
    + .name = "gcc_crypto_ahb_clk",
    + .parent_names = (const char *[]){
    + "pcnoc_clk_src"
    + },
    + .num_parents = 1,
    + .flags = CLK_SET_RATE_PARENT,
    + .ops = &clk_branch2_ops,
    + },
    + },
    +};
    +
    +static struct clk_branch gcc_crypto_axi_clk = {
    + .halt_reg = 0x16020,
    + .halt_check = BRANCH_HALT_VOTED,
    + .clkr = {
    + .enable_reg = 0x0b004,
    + .enable_mask = BIT(1),
    + .hw.init = &(struct clk_init_data){
    + .name = "gcc_crypto_axi_clk",
    + .parent_names = (const char *[]){
    + "pcnoc_clk_src"
    + },
    + .num_parents = 1,
    + .flags = CLK_SET_RATE_PARENT,
    + .ops = &clk_branch2_ops,
    + },
    + },
    +};
    +
    +static struct clk_branch gcc_crypto_clk = {
    + .halt_reg = 0x1601c,
    + .halt_check = BRANCH_HALT_VOTED,
    + .clkr = {
    + .enable_reg = 0x0b004,
    + .enable_mask = BIT(2),
    + .hw.init = &(struct clk_init_data){
    + .name = "gcc_crypto_clk",
    + .parent_names = (const char *[]){
    + "crypto_clk_src"
    + },
    + .num_parents = 1,
    + .flags = CLK_SET_RATE_PARENT,
    + .ops = &clk_branch2_ops,
    + },
    + },
    +};
    +
    +static struct clk_branch gcc_gp1_clk = {
    + .halt_reg = 0x08000,
    + .clkr = {
    + .enable_reg = 0x08000,
    + .enable_mask = BIT(0),
    + .hw.init = &(struct clk_init_data){
    + .name = "gcc_gp1_clk",
    + .parent_names = (const char *[]){
    + "gp1_clk_src"
    + },
    + .num_parents = 1,
    + .flags = CLK_SET_RATE_PARENT,
    + .ops = &clk_branch2_ops,
    + },
    + },
    +};
    +
    +static struct clk_branch gcc_gp2_clk = {
    + .halt_reg = 0x09000,
    + .clkr = {
    + .enable_reg = 0x09000,
    + .enable_mask = BIT(0),
    + .hw.init = &(struct clk_init_data){
    + .name = "gcc_gp2_clk",
    + .parent_names = (const char *[]){
    + "gp2_clk_src"
    + },
    + .num_parents = 1,
    + .flags = CLK_SET_RATE_PARENT,
    + .ops = &clk_branch2_ops,
    + },
    + },
    +};
    +
    +static struct clk_branch gcc_gp3_clk = {
    + .halt_reg = 0x0a000,
    + .clkr = {
    + .enable_reg = 0x0a000,
    + .enable_mask = BIT(0),
    + .hw.init = &(struct clk_init_data){
    + .name = "gcc_gp3_clk",
    + .parent_names = (const char *[]){
    + "gp3_clk_src"
    + },
    + .num_parents = 1,
    + .flags = CLK_SET_RATE_PARENT,
    + .ops = &clk_branch2_ops,
    + },
    + },
    +};
    +
    static struct clk_hw *gcc_ipq8074_hws[] = {
    &gpll0_out_main_div2.hw,
    &gpll6_out_main_div2.hw,
    @@ -4233,6 +4422,10 @@ enum {
    [NSS_PORT6_RX_DIV_CLK_SRC] = &nss_port6_rx_div_clk_src.clkr,
    [NSS_PORT6_TX_CLK_SRC] = &nss_port6_tx_clk_src.clkr,
    [NSS_PORT6_TX_DIV_CLK_SRC] = &nss_port6_tx_div_clk_src.clkr,
    + [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
    + [GP1_CLK_SRC] = &gp1_clk_src.clkr,
    + [GP2_CLK_SRC] = &gp2_clk_src.clkr,
    + [GP3_CLK_SRC] = &gp3_clk_src.clkr,
    [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
    [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
    [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
    @@ -4362,6 +4555,12 @@ enum {
    [GCC_UNIPHY1_PORT5_TX_CLK] = &gcc_uniphy1_port5_tx_clk.clkr,
    [GCC_UNIPHY2_PORT6_RX_CLK] = &gcc_uniphy2_port6_rx_clk.clkr,
    [GCC_UNIPHY2_PORT6_TX_CLK] = &gcc_uniphy2_port6_tx_clk.clkr,
    + [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
    + [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
    + [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
    + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
    + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
    + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
    };

    static const struct qcom_reset_map gcc_ipq8074_resets[] = {
    --
    QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
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