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    Subject[PATCH V4 10/11] KVM: x86: Implement Intel Processor Trace MSRs read/write
    Date
    From: Chao Peng <chao.p.peng@linux.intel.com>

    Intel PT MSRs read/write will not be intercepted when guest enabled
    Intel PT. IA32_RTIT_CTL read/write will always cause a VM-Exit.

    Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
    Signed-off-by: Luwei Kang <luwei.kang@intel.com>
    ---
    arch/x86/kvm/vmx.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
    arch/x86/kvm/x86.c | 20 +++++++++++++++++
    2 files changed, 84 insertions(+)

    diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
    index d2e64bf..f948231 100644
    --- a/arch/x86/kvm/vmx.c
    +++ b/arch/x86/kvm/vmx.c
    @@ -949,6 +949,7 @@ static void vmx_get_segment(struct kvm_vcpu *vcpu,
    static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
    u16 error_code);
    static void pt_disable_intercept_for_msr(bool flag);
    +static bool vmx_pt_supported(void);

    static DEFINE_PER_CPU(struct vmcs *, vmxarea);
    static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
    @@ -3349,6 +3350,38 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
    return 1;
    msr_info->data = vcpu->arch.ia32_xss;
    break;
    + case MSR_IA32_RTIT_CTL:
    + if (!vmx_pt_supported())
    + return 1;
    + msr_info->data = to_vmx(vcpu)->pt_desc.guest.ctl;
    + break;
    + case MSR_IA32_RTIT_STATUS:
    + if (!vmx_pt_supported())
    + return 1;
    + msr_info->data = to_vmx(vcpu)->pt_desc.guest.status;
    + break;
    + case MSR_IA32_RTIT_CR3_MATCH:
    + if (!vmx_pt_supported())
    + return 1;
    + msr_info->data = to_vmx(vcpu)->pt_desc.guest.cr3_match;
    + break;
    + case MSR_IA32_RTIT_OUTPUT_BASE:
    + if (!vmx_pt_supported())
    + return 1;
    + msr_info->data = to_vmx(vcpu)->pt_desc.guest.output_base;
    + break;
    + case MSR_IA32_RTIT_OUTPUT_MASK:
    + if (!vmx_pt_supported())
    + return 1;
    + msr_info->data = to_vmx(vcpu)->pt_desc.guest.output_mask;
    + break;
    + case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
    + if (!vmx_pt_supported())
    + return 1;
    + msr_info->data =
    + to_vmx(vcpu)->pt_desc.guest.addrs[msr_info->index -
    + MSR_IA32_RTIT_ADDR0_A];
    + break;
    case MSR_TSC_AUX:
    if (!msr_info->host_initiated &&
    !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
    @@ -3473,6 +3506,37 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
    else
    clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
    break;
    + case MSR_IA32_RTIT_CTL:
    + if (!vmx_pt_supported() || to_vmx(vcpu)->nested.vmxon)
    + return 1;
    + vmx_set_rtit_ctl(vcpu, data);
    + break;
    + case MSR_IA32_RTIT_STATUS:
    + if (!vmx_pt_supported())
    + return 1;
    + vmx->pt_desc.guest.status = data;
    + break;
    + case MSR_IA32_RTIT_CR3_MATCH:
    + if (!vmx_pt_supported())
    + return 1;
    + vmx->pt_desc.guest.cr3_match = data;
    + break;
    + case MSR_IA32_RTIT_OUTPUT_BASE:
    + if (!vmx_pt_supported())
    + return 1;
    + vmx->pt_desc.guest.output_base = data;
    + break;
    + case MSR_IA32_RTIT_OUTPUT_MASK:
    + if (!vmx_pt_supported())
    + return 1;
    + vmx->pt_desc.guest.output_mask = data;
    + break;
    + case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
    + if (!vmx_pt_supported())
    + return 1;
    + vmx->pt_desc.guest.addrs[msr_info->index -
    + MSR_IA32_RTIT_ADDR0_A] = data;
    + break;
    case MSR_TSC_AUX:
    if (!msr_info->host_initiated &&
    !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
    diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
    index b19a749..3f16626 100644
    --- a/arch/x86/kvm/x86.c
    +++ b/arch/x86/kvm/x86.c
    @@ -1022,6 +1022,12 @@ unsigned int kvm_get_pt_addr_cnt(void)
    #endif
    MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
    MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
    + MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
    + MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
    + MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
    + MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
    + MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
    + MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
    };

    static unsigned num_msrs_to_save;
    @@ -4337,6 +4343,20 @@ static void kvm_init_msr_list(void)
    if (!kvm_x86_ops->rdtscp_supported())
    continue;
    break;
    + case MSR_IA32_RTIT_CTL:
    + case MSR_IA32_RTIT_STATUS:
    + case MSR_IA32_RTIT_CR3_MATCH:
    + case MSR_IA32_RTIT_OUTPUT_BASE:
    + case MSR_IA32_RTIT_OUTPUT_MASK:
    + if (!kvm_x86_ops->pt_supported())
    + continue;
    + break;
    + case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
    + if (!kvm_x86_ops->pt_supported() || msrs_to_save[i] -
    + MSR_IA32_RTIT_ADDR0_A >= kvm_get_pt_addr_cnt())
    + continue;
    + break;
    + }
    default:
    break;
    }
    --
    1.8.3.1
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