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Subject[PATCH 03/30] x86, mm: document X86_CR4_PGE toggling behavior
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From: Dave Hansen <dave.hansen@linux.intel.com>

The comment says it all here. The problem here is that the
X86_CR4_PGE bit affects all PCIDs in a way that is totally
obscure.

This makes it easier for someone to find if grepping for PCID-
related stuff and documents the hardware behavior that we are
depending on.

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Moritz Lipp <moritz.lipp@iaik.tugraz.at>
Cc: Daniel Gruss <daniel.gruss@iaik.tugraz.at>
Cc: Michael Schwarz <michael.schwarz@iaik.tugraz.at>
Cc: Richard Fellner <richard.fellner@student.tugraz.at>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Kees Cook <keescook@google.com>
Cc: Hugh Dickins <hughd@google.com>
Cc: x86@kernel.org
---

b/arch/x86/include/asm/tlbflush.h | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)

diff -puN arch/x86/include/asm/tlbflush.h~kaiser-prep-document-cr4-pge-behavior arch/x86/include/asm/tlbflush.h
--- a/arch/x86/include/asm/tlbflush.h~kaiser-prep-document-cr4-pge-behavior 2017-11-08 10:45:26.994681401 -0800
+++ b/arch/x86/include/asm/tlbflush.h 2017-11-08 10:45:26.997681401 -0800
@@ -257,10 +257,12 @@ static inline void __native_flush_tlb_gl
*/
WARN_ON_ONCE(!(cr4 & X86_CR4_PGE));
/*
- * Architecturally, any _change_ to X86_CR4_PGE will fully flush the
- * TLB of all entries including all entries in all PCIDs and all
- * global pages. Make sure that we _change_ the bit, regardless of
+ * Architecturally, any _change_ to X86_CR4_PGE will fully flush
+ * all entries. Make sure that we _change_ the bit, regardless of
* whether we had X86_CR4_PGE set in the first place.
+ *
+ * Note that just toggling PGE *also* flushes all entries from all
+ * PCIDs, regardless of the state of X86_CR4_PCIDE.
*/
native_write_cr4(cr4 ^ X86_CR4_PGE);
/* Put original CR4 value back: */
_
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