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    SubjectRe: [PATCH 08/31] nds32: Cache and TLB routines
    On Wed, Nov 8, 2017 at 6:54 AM, Greentime Hu <green.hu@gmail.com> wrote:

    > +#ifndef __NDS32_PROCFNS_H__
    > +#define __NDS32_PROCFNS_H__
    > +
    > +#define CPU_NAME n13
    > +
    > +#ifdef __KERNEL__
    > +
    > +#ifdef __STDC__
    > +#define ____cpu_fn(name,fn) name##fn
    > +#else
    > +#define ____cpu_fn(name,fn) name/**/fn
    > +#endif
    > +#define __cpu_fn(name,fn) ____cpu_fn(name,fn)
    > +
    > +#define cpu_proc_init __cpu_fn( CPU_NAME, _proc_init)
    > +#define cpu_proc_fin __cpu_fn( CPU_NAME, _proc_fin)
    > +#define cpu_do_idle __cpu_fn( CPU_NAME, _do_idle)
    > +#define cpu_reset __cpu_fn( CPU_NAME, _reset)
    > +#define cpu_switch_mm __cpu_fn( CPU_NAME, _switch_mm)

    I see you have copied this from ARM. Do you actually need the same complexity,
    with the ability to build either optimal code for a particular CPU or
    a multi-CPU
    version?

    Most other architectures seem to have settled for doing just one of the two
    models. How many CPU implementations to you expect to support that
    differ in all of those functions?

    Arnd

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