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    Subject[PATCH AUTOSEL for 4.9 29/56] clk: qcom: ipq4019: Add all the frequencies for apss cpu
    Date
    From: Abhishek Sahu <absahu@codeaurora.org>

    [ Upstream commit 86c654d41a52e3d17e9bc2c2ba37f3c963e66a4a ]

    The APSS CPU clock does not contain all the frequencies in its
    frequency table so this patch adds the same.

    Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
    Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
    Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
    ---
    drivers/clk/qcom/gcc-ipq4019.c | 14 ++++++++++++--
    1 file changed, 12 insertions(+), 2 deletions(-)

    diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
    index b593065de8db..8ab6ce4d976f 100644
    --- a/drivers/clk/qcom/gcc-ipq4019.c
    +++ b/drivers/clk/qcom/gcc-ipq4019.c
    @@ -525,10 +525,20 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
    };

    static const struct freq_tbl ftbl_gcc_apps_clk[] = {
    - F(48000000, P_XO, 1, 0, 0),
    + F(48000000, P_XO, 1, 0, 0),
    F(200000000, P_FEPLL200, 1, 0, 0),
    + F(384000000, P_DDRPLLAPSS, 1, 0, 0),
    + F(413000000, P_DDRPLLAPSS, 1, 0, 0),
    + F(448000000, P_DDRPLLAPSS, 1, 0, 0),
    + F(488000000, P_DDRPLLAPSS, 1, 0, 0),
    F(500000000, P_FEPLL500, 1, 0, 0),
    - F(626000000, P_DDRPLLAPSS, 1, 0, 0),
    + F(512000000, P_DDRPLLAPSS, 1, 0, 0),
    + F(537000000, P_DDRPLLAPSS, 1, 0, 0),
    + F(565000000, P_DDRPLLAPSS, 1, 0, 0),
    + F(597000000, P_DDRPLLAPSS, 1, 0, 0),
    + F(632000000, P_DDRPLLAPSS, 1, 0, 0),
    + F(672000000, P_DDRPLLAPSS, 1, 0, 0),
    + F(716000000, P_DDRPLLAPSS, 1, 0, 0),
    { }
    };

    --
    2.11.0
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