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SubjectRe: [PATCH 21/30] x86, mm: put mmu-to-h/w ASID translation in one place
On Fri, Nov 10, 2017 at 11:31 AM, Dave Hansen
<dave.hansen@linux.intel.com> wrote:
>
> From: Dave Hansen <dave.hansen@linux.intel.com>
>
> There are effectively two ASID types:
> 1. The one stored in the mmu_context that goes from 0->5
> 2. The one programmed into the hardware that goes from 1->6
>
> This consolidates the locations where converting beween the two
> (by doing +1) to a single place which gives us a nice place to
> comment. KAISER will also need to, given an ASID, know which
> hardware ASID to flush for the userspace mapping.
>
> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
> Cc: Moritz Lipp <moritz.lipp@iaik.tugraz.at>
> Cc: Daniel Gruss <daniel.gruss@iaik.tugraz.at>
> Cc: Michael Schwarz <michael.schwarz@iaik.tugraz.at>
> Cc: Richard Fellner <richard.fellner@student.tugraz.at>
> Cc: Andy Lutomirski <luto@kernel.org>
> Cc: Linus Torvalds <torvalds@linux-foundation.org>
> Cc: Kees Cook <keescook@google.com>
> Cc: Hugh Dickins <hughd@google.com>
> Cc: x86@kernel.org
> ---
>
> b/arch/x86/include/asm/tlbflush.h | 30 ++++++++++++++++++------------
> 1 file changed, 18 insertions(+), 12 deletions(-)
>
> diff -puN arch/x86/include/asm/tlbflush.h~kaiser-pcid-pre-build-kern arch/x86/include/asm/tlbflush.h
> --- a/arch/x86/include/asm/tlbflush.h~kaiser-pcid-pre-build-kern 2017-11-10 11:22:16.521244931 -0800
> +++ b/arch/x86/include/asm/tlbflush.h 2017-11-10 11:22:16.525244931 -0800
> @@ -87,21 +87,26 @@ static inline u64 inc_mm_tlb_gen(struct
> */
> #define MAX_ASID_AVAILABLE ((1<<CR3_AVAIL_ASID_BITS) - 2)
>
> -/*
> - * If PCID is on, ASID-aware code paths put the ASID+1 into the PCID
> - * bits. This serves two purposes. It prevents a nasty situation in
> - * which PCID-unaware code saves CR3, loads some other value (with PCID
> - * == 0), and then restores CR3, thus corrupting the TLB for ASID 0 if
> - * the saved ASID was nonzero. It also means that any bugs involving
> - * loading a PCID-enabled CR3 with CR4.PCIDE off will trigger
> - * deterministically.
> - */
> +static inline u16 kern_asid(u16 asid)
> +{
> + VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
> + /*
> + * If PCID is on, ASID-aware code paths put the ASID+1 into the PCID
> + * bits. This serves two purposes. It prevents a nasty situation in
> + * which PCID-unaware code saves CR3, loads some other value (with PCID
> + * == 0), and then restores CR3, thus corrupting the TLB for ASID 0 if
> + * the saved ASID was nonzero. It also means that any bugs involving
> + * loading a PCID-enabled CR3 with CR4.PCIDE off will trigger
> + * deterministically.
> + */
> + return asid + 1;
> +}

This seems really error-prone. Maybe we should have a pcid_t type and
make all the interfaces that want a h/w PCID take pcid_t.

--Andy

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