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Subject[PATCH 02/30] x86, tlb: Make CR4-based TLB flushes more robust
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From: Dave Hansen <dave.hansen@linux.intel.com>

The existing CR4-based TLB flush currently requires global pages
to be supported *and* enabled. But, the hardware only needs for
them to be supported.

Make the code more robust by allowing the initial state of
X86_CR4_PGE to be on *or* off. In addition, if called in an
unexpected state (X86_CR4_PGE=0), issue a warning. X86_CR4_PGE=0
is certainly unexpected should not be ignored it if encountered.

This essentially gives the best of both worlds: a TLB flush no
matter what, and a warning if the TLB flush is called in an
unexpected way (X86_CR4_PGE=0).

The XOR change was suggested by Kirill Shutemov.

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Moritz Lipp <moritz.lipp@iaik.tugraz.at>
Cc: Daniel Gruss <daniel.gruss@iaik.tugraz.at>
Cc: Michael Schwarz <michael.schwarz@iaik.tugraz.at>
Cc: Richard Fellner <richard.fellner@student.tugraz.at>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Kees Cook <keescook@google.com>
Cc: Hugh Dickins <hughd@google.com>
Cc: x86@kernel.org
---

b/arch/x86/include/asm/tlbflush.h | 22 +++++++++++++++++-----
1 file changed, 17 insertions(+), 5 deletions(-)

diff -puN arch/x86/include/asm/tlbflush.h~kaiser-prep-make-cr4-writes-tolerate-clear-pge arch/x86/include/asm/tlbflush.h
--- a/arch/x86/include/asm/tlbflush.h~kaiser-prep-make-cr4-writes-tolerate-clear-pge 2017-11-10 11:22:05.534244958 -0800
+++ b/arch/x86/include/asm/tlbflush.h 2017-11-10 11:22:05.538244958 -0800
@@ -247,12 +247,24 @@ static inline void __native_flush_tlb(vo

static inline void __native_flush_tlb_global_irq_disabled(void)
{
- unsigned long cr4;
+ unsigned long cr4 = this_cpu_read(cpu_tlbstate.cr4);

- cr4 = this_cpu_read(cpu_tlbstate.cr4);
- /* clear PGE */
- native_write_cr4(cr4 & ~X86_CR4_PGE);
- /* write old PGE again and flush TLBs */
+ /*
+ * This function is only called on systems that support X86_CR4_PGE
+ * and where we expect X86_CR4_PGE to be set. Warn if we are called
+ * without PGE set.
+ */
+ WARN_ON_ONCE(!(cr4 & X86_CR4_PGE));
+
+ /*
+ * Architecturally, any _change_ to X86_CR4_PGE will fully flush the
+ * TLB of all entries including all entries in all PCIDs and all
+ * global pages. Make sure that we _change_ the bit, regardless of
+ * whether we had X86_CR4_PGE set in the first place.
+ */
+ native_write_cr4(cr4 ^ X86_CR4_PGE);
+
+ /* Put original CR4 value back: */
native_write_cr4(cr4);
}

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