| From | Ben Hutchings <> | Date | Mon, 09 Oct 2017 13:44:24 +0100 | Subject | [PATCH 3.16 070/192] MIPS: Actually decode JALX in `__compute_return_epc_for_insn' |
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3.16.49-rc1 review patch. If anyone has any objections, please let me know.
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From: "Maciej W. Rozycki" <macro@imgtec.com>
commit a9db101b735a9d49295326ae41f610f6da62b08c upstream.
Complement commit fb6883e5809c ("MIPS: microMIPS: Support handling of delay slots.") and actually decode the regular MIPS JALX major instruction opcode, the handling of which has been added with the said commit for EPC calculation in `__compute_return_epc_for_insn'.
Fixes: fb6883e5809c ("MIPS: microMIPS: Support handling of delay slots.") Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16394/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Ben Hutchings <ben@decadent.org.uk> --- arch/mips/kernel/branch.c | 1 + 1 file changed, 1 insertion(+)
--- a/arch/mips/kernel/branch.c +++ b/arch/mips/kernel/branch.c @@ -493,6 +493,7 @@ int __compute_return_epc_for_insn(struct /* * These are unconditional and in j_format. */ + case jalx_op: case jal_op: regs->regs[31] = regs->cp0_epc + 8; case j_op:
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