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SubjectRe: [PATCH 4/4] irqchip: imgpdc: Pass on peripheral mask/unmasks to the parent
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On 04/10/17 15:03, James Hogan wrote:
> Hi Ed,
>
> On Mon, Oct 02, 2017 at 10:55:59AM +0100, Ed Blake wrote:
>> Pass on peripheral (RTC/IR/WD) irq masks and unmasks to the parent
>> interrupt controller, as well as setting / clearing the relevant bits
>> in the IRQ_ROUTE register.
>>
>> Clearing bits in the IRQ_ROUTE register will prevent future interrupts
>> from being passed on to the parent, but won't mask an existing
>> interrupt which has already made it to the parent.
> Is it an edge or level sensitive interrupt from the PDC?

It's level triggered.

> I'm a little rusty on the IRQ subsystem TBH, but if edge sensitive I
> would have expected the parent interrupt to be acked/cleared by the
> parent handler.
>
> And if level sensitive I would have expected the deasserted parent
> interrupt to be masked by the parent handler, and immediately cleared
> upon rerouting.
>
> Maybe you can clarify whats going on here.

I'm not sure how this is supposed to work, but the issue seems to be
that without this patch the parent irq isn't being masked.  This is
causing the parent handler (MIPS GIC in this case) to be called
continuously.  This leads to the PDC irq being masked each time, but not
the parent irq.  This is the callstack:

    "irq-imgpdc.c"::perip_irq_mask
    mask_ack_irq
    handle_level_irq
    generic_handle_irq_desc
    generic_handle_irq
    generic_handle_irq_desc
    generic_handle_irq
    gic_handle_shared_int
    gic_handle_local_int
    "irq-mips-gic.c"::gic_irq_dispatch
    generic_handle_irq_desc
    generic_handle_irq
    do_IRQ
    plat_irq_dispatch()

Ed.

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