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SubjectRe: [PATCH v3 07/14] xhci: Add Intel cherrytrail extended cap / otg phy mux handling
On 22.09.2017 21:37, Hans de Goede wrote:
> The Intel cherrytrail xhci controller has an extended cap mmio-range
> which contains registers to control the muxing to the xhci (host mode)
> or the dwc3 (device mode) and vbus-detection for the otg usb-phy.
> Having a mux driver included in the xhci code (or under drivers/usb/host)
> is not desirable. So this commit adds a simple handler for this extended
> capability, which creates a platform device with the caps mmio region as
> resource, this allows us to write a separate platform mux driver for the
> mux.
> Note this commit adds a call to the new xhci_ext_cap_init() function
> to xhci_pci_probe(), it is added here because xhci_ext_cap_init() must
> be called only once. If in the future we also want to handle ext-caps
> on non pci XHCI HCDs from xhci_ext_cap_init() a call to it should also
> be added to other bus probe paths.
> Signed-off-by: Hans de Goede <>
> ---
> Changes in v2:
> -Check xHCI controller PCI device-id instead of only checking for the
> Intel Extended capability ID, as the Extended capability ID is used on
> other model Intel xHCI controllers too
> Changes in v3:
> -Add a new generic xhci_ext_cap_init() function and handle the new
> XHCI_INTEL_CHT_USB_MUX quirk there.
> ---

Acked-by: Mathias Nyman <>

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