Messages in this thread | | | Date | Tue, 3 Oct 2017 19:28:34 +0200 | From | Radim Krčmář <> | Subject | Re: [PATCH v2 3/4] KVM: LAPIC: Apply change to TDCR right away to the timer |
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2017-09-28 18:04-0700, Wanpeng Li: > From: Wanpeng Li <wanpeng.li@hotmail.com> > > The description in the Intel SDM of how the divide configuration > register is used: "The APIC timer frequency will be the processor's bus > clock or core crystal clock frequency divided by the value specified in > the divide configuration register." > > Observation of baremetal shown that when the TDCR is change, the TMCCT > does not change or make a big jump in value, but the rate at which it > count down change. > > The patch update the emulation to APIC timer to so that a change to the > divide configuration would be reflected in the value of the counter and > when the next interrupt is triggered. > > Cc: Paolo Bonzini <pbonzini@redhat.com> > Cc: Radim Krčmář <rkrcmar@redhat.com> > Signed-off-by: Wanpeng Li <wanpeng.li@hotmail.com> > ---
Why do we need to do more than just restart the timer?
The TMCCT should remain roughly at the same level -- changing divide count modifies target_expiration and it looks like apic_get_tmcct() would get the same result like before changing divide count.
Thanks.
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