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SubjectRe: [PATCH v2 3/4] KVM: LAPIC: Apply change to TDCR right away to the timer
2017-10-04 1:28 GMT+08:00 Radim Krčmář <>:
> 2017-09-28 18:04-0700, Wanpeng Li:
>> From: Wanpeng Li <>
>> The description in the Intel SDM of how the divide configuration
>> register is used: "The APIC timer frequency will be the processor's bus
>> clock or core crystal clock frequency divided by the value specified in
>> the divide configuration register."
>> Observation of baremetal shown that when the TDCR is change, the TMCCT
>> does not change or make a big jump in value, but the rate at which it
>> count down change.
>> The patch update the emulation to APIC timer to so that a change to the
>> divide configuration would be reflected in the value of the counter and
>> when the next interrupt is triggered.
>> Cc: Paolo Bonzini <>
>> Cc: Radim Krčmář <>
>> Signed-off-by: Wanpeng Li <>
>> ---
> Why do we need to do more than just restart the timer?

Because the current timer (hv or sw) are still running. I think the
goal of this commit is to runtime update the rate of the current timer
which is running. Our restart_apic_timer() implementation just cancels
the current timer when switch between preemption timer and hrtimer.

Wanpeng Li

> The TMCCT should remain roughly at the same level -- changing divide
> count modifies target_expiration and it looks like apic_get_tmcct()
> would get the same result like before changing divide count.
> Thanks.

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