Messages in this thread | | | Subject | Re: Need clarity on PCIe MSI interrupt in device tree | From | valmiki <> | Date | Wed, 4 Jan 2017 22:59:48 +0530 |
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Thanks Mark
On 1/4/2017 3:35 PM, Mark Rutland wrote: > On Wed, Jan 04, 2017 at 08:47:43AM +0530, valmiki wrote: >> Hi, > > Hi, > >> I have confusion on MSI interrupt flags in PCIe documetation. >> >> MSI interrupts are edge triggered, but i see some controllers use >> Ex:tegra <0 99 0x4>, here interrupt flags show 0x4 which means level >> sensitive as per include/dt-bindings/interrupt-controller/irq.h. > > As Marc says, this isn't actually a description of an MSI, but rather > the interrupt generated by the interrupt controller, which is often (but > not always) built into PCIe host controllers. > > This looks something like: > > +--------+ +-----------------+ +----------+ > | | +----------+ |~~msi~irq~~>| | > | Device |==MSI==>| MSI ctrl | PCIe | | IRQ ctrl |~~~> CPU > | | +----------+ |~~intx~irq~>| | > +--------+ +-----------------+ +----------+ > > Each PCIe device sends MSIs to the MSI controller. In response to this, > the MSI controller raises a wired interrupt, which is named "msi" in the > DT binding because it is the interrupt generated by the MSI controller, > and the PCIe controller may raise several distinct interrupts which all > need names. > >> May i know why is it like this, why MSI depicted as level sensitive >> in device tree. > > As above, the interrupt from the MSI controller to the interrupt > controller is level sensitive, but this is not the case for the actual > MSIs. > > Thanks, > Mark. >
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