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    Subject[PATCH 4.9 056/130] powerpc: Ignore reserved field in DCSR and PVR reads and writes
    Date
    4.9-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Anton Blanchard <anton@samba.org>

    commit 178f358208ceb8b38e5cff3f815e0db4a6a70a07 upstream.

    IBM bit 31 (for the rest of us - bit 0) is a reserved field in the
    instruction definition of mtspr and mfspr. Hardware is encouraged to
    (and does) ignore it.

    As a result, if userspace executes an mtspr DSCR with the reserved bit
    set, we get a DSCR facility unavailable exception. The kernel fails to
    match against the expected value/mask, and we silently return to
    userspace to try and re-execute the same mtspr DSCR instruction. We
    loop forever until the process is killed.

    We should do something here, and it seems mirroring what hardware does
    is the better option vs killing the process. While here, relax the
    matching of mfspr PVR too.

    Signed-off-by: Anton Blanchard <anton@samba.org>
    Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    arch/powerpc/include/asm/ppc-opcode.h | 10 +++++-----
    1 file changed, 5 insertions(+), 5 deletions(-)

    --- a/arch/powerpc/include/asm/ppc-opcode.h
    +++ b/arch/powerpc/include/asm/ppc-opcode.h
    @@ -157,7 +157,7 @@
    #define PPC_INST_MCRXR 0x7c000400
    #define PPC_INST_MCRXR_MASK 0xfc0007fe
    #define PPC_INST_MFSPR_PVR 0x7c1f42a6
    -#define PPC_INST_MFSPR_PVR_MASK 0xfc1fffff
    +#define PPC_INST_MFSPR_PVR_MASK 0xfc1ffffe
    #define PPC_INST_MFTMR 0x7c0002dc
    #define PPC_INST_MSGSND 0x7c00019c
    #define PPC_INST_MSGCLR 0x7c0001dc
    @@ -174,13 +174,13 @@
    #define PPC_INST_RFDI 0x4c00004e
    #define PPC_INST_RFMCI 0x4c00004c
    #define PPC_INST_MFSPR_DSCR 0x7c1102a6
    -#define PPC_INST_MFSPR_DSCR_MASK 0xfc1fffff
    +#define PPC_INST_MFSPR_DSCR_MASK 0xfc1ffffe
    #define PPC_INST_MTSPR_DSCR 0x7c1103a6
    -#define PPC_INST_MTSPR_DSCR_MASK 0xfc1fffff
    +#define PPC_INST_MTSPR_DSCR_MASK 0xfc1ffffe
    #define PPC_INST_MFSPR_DSCR_USER 0x7c0302a6
    -#define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1fffff
    +#define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1ffffe
    #define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6
    -#define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1fffff
    +#define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1ffffe
    #define PPC_INST_MFVSRD 0x7c000066
    #define PPC_INST_MTVSRD 0x7c000166
    #define PPC_INST_SLBFEE 0x7c0007a7

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