Messages in this thread Patch in this message | | | Subject | [PATCH 13/13] libnvdimm, pmem: disable dax flushing for 'cache flush on fail' platforms | From | Dan Williams <> | Date | Thu, 19 Jan 2017 19:51:23 -0800 |
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There are platforms that arrange for caches to be flushed on a power fail event. When the platform has this capability it is redundant to spend cycles flushing caches at fsync(). Provide a libnvdimm module parameter to override the default flushing behavior since there is no other mechanism defined to detect this platform property.
Cc: Jan Kara <jack@suse.cz> Cc: Jeff Moyer <jmoyer@redhat.com> Cc: Christoph Hellwig <hch@lst.de> Cc: Matthew Wilcox <mawilcox@microsoft.com> Cc: Ross Zwisler <ross.zwisler@linux.intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> --- drivers/nvdimm/region_devs.c | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/drivers/nvdimm/region_devs.c b/drivers/nvdimm/region_devs.c index ef32b938023e..4cc7fbc4f13f 100644 --- a/drivers/nvdimm/region_devs.c +++ b/drivers/nvdimm/region_devs.c @@ -11,6 +11,7 @@ * General Public License for more details. */ #include <linux/scatterlist.h> +#include <linux/moduleparam.h> #include <linux/highmem.h> #include <linux/sched.h> #include <linux/slab.h> @@ -21,6 +22,11 @@ #include "nd-core.h" #include "nd.h" +static bool platform_has_flush_on_fail; +module_param(platform_has_flush_on_fail, bool, 00444); +MODULE_PARM_DESC(platform_has_flush_on_fail, + "Platform arranges for cpu caches to be flushed on power failure"); + /* * For readq() and writeq() on 32-bit builds, the hi-lo, lo-hi order is * irrelevant. @@ -963,6 +969,11 @@ int nvdimm_has_flush(struct nd_region *nd_region) struct nd_region_data *ndrd = dev_get_drvdata(&nd_region->dev); int i; + if (platform_has_flush_on_fail) { + pr_info_once("libnvdimm.platform_has_flush_on_fail enabled\n"); + return -EINVAL; + } + if (is_nd_volatile(&nd_region->dev)) return -EINVAL;
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