Re: [PATCH] clk: rockchip: fix the incorrect pclk_edp div width for RK3399
Date
Wed, 18 Jan 2017 11:25:21 +0100
Am Mittwoch, 18. Januar 2017, 12:20:56 CET schrieb Xing Zheng: > The range of the pclk_edp_div_con is [13:8] and 6 bits, not 5. > > Reported-by: Lin Huang <hl@rock-chips.com> > Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>