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SubjectRE: eMMC boot problem: switch to bus width 8 ddr failed
Date
> -----Original Message-----
> From: Ulf Hansson [mailto:ulf.hansson@linaro.org]
> Sent: Friday, January 13, 2017 7:23 PM
> To: Bough Chen <haibo.chen@nxp.com>
> Cc: Shawn Lin <shawn.lin@rock-chips.com>; Clemens Gruber
> <clemens.gruber@pqgruber.com>; linux-mmc@vger.kernel.org; Linus Walleij
> <linus.walleij@linaro.org>; Adrian Hunter <adrian.hunter@intel.com>; A.S.
> Dong <aisheng.dong@nxp.com>; linux-kernel@vger.kernel.org; Gary Bisson
> <gary.bisson@boundarydevices.com>; Fabio Estevam <festevam@gmail.com>;
> Shawn Guo <shawnguo@kernel.org>
> Subject: Re: eMMC boot problem: switch to bus width 8 ddr failed
>
> [...]
>
> > Hi Ulf and Shawn,
> >
> > Aisheng and I debug this issue these days, and we find the root cause.
> > There are two things to describe.
> >
> > 1) voltage switch issue. The properity "no-1-8-v" do not work for
> MMC_TIMING_MMC_DDR52.
> > This is another bug, we need to fix, but has no relation with the current bug.
>
> I am working on a patch which invents MMC_CAP_3_3V_DDR and which has a
> corresponding DT binding "mmc-ddr-3_3v".
> Give me a day or so, then I will post it.
>
> Likely it should help to resolve your issue, don't you think?

Seems Yes, I will test the patch when you post.

Best Regards,
Haibo Chen

>
> [...]
>
> Kind regards
> Uffe
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