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    Subject[PATCH v2 07/33] x86/intel_rdt: Add support for Cache Allocation detection
    Date
    From: Vikas Shivappa <vikas.shivappa@linux.intel.com>

    This patch includes CPUID enumeration routines for Cache allocation and
    new values to track resources to the cpuinfo_x86 structure.

    Cache allocation provides a way for the Software (OS/VMM) to restrict
    cache allocation to a defined 'subset' of cache which may be overlapping
    with other 'subsets'. This feature is used when allocating a line in
    cache ie when pulling new data into the cache. The programming of the
    hardware is done via programming MSRs (model specific registers).

    Signed-off-by: Vikas Shivappa <vikas.shivappa@linux.intel.com>
    Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
    Reviewed-by: Tony Luck <tony.luck@intel.com>
    ---
    arch/x86/include/asm/cpufeature.h | 8 +++++--
    arch/x86/include/asm/cpufeatures.h | 6 +++++-
    arch/x86/include/asm/disabled-features.h | 3 ++-
    arch/x86/include/asm/processor.h | 3 +++
    arch/x86/include/asm/required-features.h | 3 ++-
    arch/x86/kernel/cpu/common.c | 19 ++++++++++++++++
    arch/x86/kernel/cpu/intel_rdt.c | 37 ++++++++++++++++++++++++++++++++
    7 files changed, 74 insertions(+), 5 deletions(-)
    create mode 100644 arch/x86/kernel/cpu/intel_rdt.c

    diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
    index 1d2b69f..9985b4cf 100644
    --- a/arch/x86/include/asm/cpufeature.h
    +++ b/arch/x86/include/asm/cpufeature.h
    @@ -28,6 +28,8 @@ enum cpuid_leafs
    CPUID_8000_000A_EDX,
    CPUID_7_ECX,
    CPUID_8000_0007_EBX,
    + CPUID_10_0_EBX,
    + CPUID_10_1_ECX,
    };

    #ifdef CONFIG_X86_FEATURE_NAMES
    @@ -78,8 +80,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
    CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 15, feature_bit) || \
    CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 16, feature_bit) || \
    CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) || \
    + CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) || \
    REQUIRED_MASK_CHECK || \
    - BUILD_BUG_ON_ZERO(NCAPINTS != 18))
    + BUILD_BUG_ON_ZERO(NCAPINTS != 19))

    #define DISABLED_MASK_BIT_SET(feature_bit) \
    ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 0, feature_bit) || \
    @@ -100,8 +103,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
    CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 15, feature_bit) || \
    CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 16, feature_bit) || \
    CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) || \
    + CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) || \
    DISABLED_MASK_CHECK || \
    - BUILD_BUG_ON_ZERO(NCAPINTS != 18))
    + BUILD_BUG_ON_ZERO(NCAPINTS != 19))

    #define cpu_has(c, bit) \
    (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
    diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
    index 92a8308..62d979b9 100644
    --- a/arch/x86/include/asm/cpufeatures.h
    +++ b/arch/x86/include/asm/cpufeatures.h
    @@ -12,7 +12,7 @@
    /*
    * Defines x86 CPU feature bits
    */
    -#define NCAPINTS 18 /* N 32-bit words worth of info */
    +#define NCAPINTS 19 /* N 32-bit words worth of info */
    #define NBUGINTS 1 /* N 32-bit bug flags */

    /*
    @@ -220,6 +220,7 @@
    #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */
    #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */
    #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */
    +#define X86_FEATURE_RDT ( 9*32+15) /* Resource Director Technology */
    #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */
    #define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */
    #define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
    @@ -286,6 +287,9 @@
    #define X86_FEATURE_SUCCOR (17*32+1) /* Uncorrectable error containment and recovery */
    #define X86_FEATURE_SMCA (17*32+3) /* Scalable MCA */

    +/* Intel-defined CPU features, CPUID level 0x00000010:0 (ebx), word 18 */
    +#define X86_FEATURE_CAT_L3 (18*32+ 1) /* Cache Allocation L3 */
    +
    /*
    * BUG word(s)
    */
    diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h
    index 85599ad..8b45e08 100644
    --- a/arch/x86/include/asm/disabled-features.h
    +++ b/arch/x86/include/asm/disabled-features.h
    @@ -57,6 +57,7 @@
    #define DISABLED_MASK15 0
    #define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE)
    #define DISABLED_MASK17 0
    -#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)
    +#define DISABLED_MASK18 0
    +#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)

    #endif /* _ASM_X86_DISABLED_FEATURES_H */
    diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
    index 63def95..e940b2d 100644
    --- a/arch/x86/include/asm/processor.h
    +++ b/arch/x86/include/asm/processor.h
    @@ -119,6 +119,9 @@ struct cpuinfo_x86 {
    int x86_cache_occ_scale; /* scale to bytes */
    int x86_power;
    unsigned long loops_per_jiffy;
    + /* Cache Allocation values: */
    + u16 x86_l3_max_cbm_len;
    + u16 x86_l3_max_closid;
    /* cpuid returned max cores value: */
    u16 x86_max_cores;
    u16 apicid;
    diff --git a/arch/x86/include/asm/required-features.h b/arch/x86/include/asm/required-features.h
    index fac9a5c..6847d85 100644
    --- a/arch/x86/include/asm/required-features.h
    +++ b/arch/x86/include/asm/required-features.h
    @@ -100,6 +100,7 @@
    #define REQUIRED_MASK15 0
    #define REQUIRED_MASK16 0
    #define REQUIRED_MASK17 0
    -#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)
    +#define REQUIRED_MASK18 0
    +#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)

    #endif /* _ASM_X86_REQUIRED_FEATURES_H */
    diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
    index 809eda0..997d1d5 100644
    --- a/arch/x86/kernel/cpu/common.c
    +++ b/arch/x86/kernel/cpu/common.c
    @@ -711,6 +711,25 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
    }
    }

    + /* Additional Intel-defined flags: level 0x00000010 */
    + if (c->cpuid_level >= 0x00000010) {
    + u32 eax, ebx, ecx, edx;
    +
    + cpuid_count(0x00000010, 0, &eax, &ebx, &ecx, &edx);
    + c->x86_capability[CPUID_10_0_EBX] = ebx;
    +
    + if (cpu_has(c, X86_FEATURE_CAT_L3)) {
    +
    + cpuid_count(0x00000010, 1, &eax, &ebx, &ecx, &edx);
    + c->x86_l3_max_closid = edx + 1;
    + c->x86_l3_max_cbm_len = eax + 1;
    + c->x86_capability[CPUID_10_1_ECX] = ecx;
    + } else {
    + c->x86_l3_max_closid = -1;
    + c->x86_l3_max_cbm_len = -1;
    + }
    + }
    +
    /* AMD-defined flags: level 0x80000001 */
    eax = cpuid_eax(0x80000000);
    c->extended_cpuid_level = eax;
    diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
    new file mode 100644
    index 0000000..fcd0642
    --- /dev/null
    +++ b/arch/x86/kernel/cpu/intel_rdt.c
    @@ -0,0 +1,37 @@
    +/*
    + * Resource Director Technology(RDT)
    + * - Cache Allocation code.
    + *
    + * Copyright (C) 2014 Intel Corporation
    + *
    + * 2015-05-25 Written by
    + * Vikas Shivappa <vikas.shivappa@intel.com>
    + *
    + * This program is free software; you can redistribute it and/or modify it
    + * under the terms and conditions of the GNU General Public License,
    + * version 2, as published by the Free Software Foundation.
    + *
    + * This program is distributed in the hope it will be useful, but WITHOUT
    + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
    + * more details.
    + *
    + * More information about RDT be found in the Intel (R) x86 Architecture
    + * Software Developer Manual June 2015, volume 3, section 17.15.
    + */
    +#include <linux/slab.h>
    +#include <linux/err.h>
    +
    +static int __init intel_rdt_late_init(void)
    +{
    + struct cpuinfo_x86 *c = &boot_cpu_data;
    +
    + if (!cpu_has(c, X86_FEATURE_CAT_L3))
    + return -ENODEV;
    +
    + pr_info("Intel cache allocation detected\n");
    +
    + return 0;
    +}
    +
    +late_initcall(intel_rdt_late_init);
    --
    2.5.0
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