Messages in this thread | | | Date | Mon, 05 Sep 2016 12:24:18 -0700 | From | Stefan Agner <> | Subject | RE: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider |
| |
On 2016-09-05 01:46, Meng Yi wrote: >> Subject: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider >> >> Since using clk_register_divider to setup the pixel clock, regmap is no longer >> used. Regmap did take care of DCU using different endianness. Check >> endianness using the device-tree property "big-endian" to determine the >> location of DIV_RATIO. >> >> Cc: stable@vger.kernel.org >> Fixes: 2d701449bce1 ("drm/fsl-dcu: use common clock framework for pixel >> clock divider") >> Reported-by: Meng Yi <meng.yi@nxp.com> >> Signed-off-by: Stefan Agner <stefan@agner.ch>
<snip>
> > Tested-by: Meng Yi <meng.yi@nxp.com> > On LS1021A-TWR board.
Thanks, applied!
-- Stefan
| |