Messages in this thread | | | Date | Fri, 30 Sep 2016 13:53:52 +0800 | From | Boqun Feng <> | Subject | Re: [PATCH locking/Documentation 1/2] Add note of release-acquire store vulnerability |
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Hi Paul,
On Thu, Sep 29, 2016 at 10:23:22AM -0700, Paul E. McKenney wrote: > On Thu, Sep 29, 2016 at 06:10:37PM +0100, Will Deacon wrote: > > On Thu, Sep 29, 2016 at 09:43:53AM -0700, Paul E. McKenney wrote: > > > On Thu, Sep 29, 2016 at 05:03:08PM +0100, Will Deacon wrote: > > > > On Thu, Sep 29, 2016 at 05:58:17PM +0200, Peter Zijlstra wrote: > > > > > On Thu, Sep 29, 2016 at 08:54:01AM -0700, Paul E. McKenney wrote: > > > > > > If two processes are related by a RELEASE+ACQUIRE pair, ordering can be > > > > > > broken if a third process overwrites the value written by the RELEASE > > > > > > operation before the ACQUIRE operation has a chance of reading it. > > > > > > This commit therefore updates the documentation to call this vulnerability > > > > > > out explicitly. > > > > > > > > > > > > Reported-by: Alan Stern <stern@rowland.harvard.edu> > > > > > > Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> > > > > > > > > > > > + However, please note that a chain of RELEASE+ACQUIRE pairs may be > > > > > > + broken by a store by another thread that overwrites the RELEASE > > > > > > + operation's store before the ACQUIRE operation's read. > > > > > > > > > > This is the powerpc lwsync quirk, right? Where the barrier disappears > > > > > when it looses the store. > > > > > > > > > > Or is there more to it? Its not entirely clear from the Changelog, which > > > > > I feel should describe the reason for the behaviour. > > > > > > > > If I've groked it correctly, it's for cases like: > > > > > > > > > > > > PO: > > > > Wx=1 > > > > WyRel=1 > > > > > > > > P1: > > > > Wy=2 > > > > > > > > P2: > > > > RyAcq=2 > > > > Rx=0 > > > > > > > > Final value of y is 2. > > > > > > > > > > > > This is permitted on arm64. If you make P1's store a store-release, then > > > > it's forbidden, but I suspect that's not generally true of the kernel > > > > memory model. > > > > > > That is the one! And to Peter's point, powerpc does the same for the > > > example as shown. However, on powerpc, upgrading P1's store to release > > > has no effect because there is no earlier access for the resulting > > > lwsync to influence. For whatever it might be worth, C11 won't guarantee > > > ordering in that case, either. Nor will the current Linux-kernel memory > > > model. (Yes, I did just try it to make sure. Why do you ask?) > > > > > > So you guys are fishing for an expanded commit log, for example, like > > > the following? ;-) > > > > > > Thanx, Paul > > > > > > ------------------------------------------------------------------------ > > > > > > If two processes are related by a RELEASE+ACQUIRE pair, ordering can be > > > broken if a third process overwrites the value written by the RELEASE > > > operation before the ACQUIRE operation has a chance of reading it, for > > > example: > > > > > > P0(int *x, int *y) > > > { > > > WRITE_ONCE(*x, 1); > > > smp_wmb(); > > > smp_store_release(y, 1); > > > } > > > > > > P1(int *y) > > > { > > > smp_store_release(y, 2); > > > } > > > > > > P2(int *x, int *y) > > > { > > > r1 = smp_load_acquire(y); > > > r2 = READ_ONCE(*x); > > > } > > > > > > Both ARM and powerpc allow the "after the dust settles" outcome (r1=2 && > > > r2=0), as does the current version of the early prototype Linux-kernel > > > memory model. > > > > FWIW, ARM doesn't allow this and arm64 only allows it if P1 uses WRITE_ONCE > > instead of store-release. > > Good catch, apologies for the error. The following, then? > > Thanx, Paul > > ------------------------------------------------------------------------ > > If two processes are related by a RELEASE+ACQUIRE pair, ordering can be > broken if a third process overwrites the value written by the RELEASE > operation before the ACQUIRE operation has a chance of reading it, for > example: > > P0(int *x, int *y) > { > WRITE_ONCE(*x, 1); > smp_wmb(); ^^^^^^^^^^^
What is this smp_wmb() for?
> smp_store_release(y, 1); > } > > P1(int *y) > { > WRITE_ONCE(*y, 2);
If we change this WRITE_ONCE to a relaxed atomic operation(e.g. xchg_relaxed(y, 2)), both herd and ppcmem said the exist-clause "y = 2 /\ 2:r1 = 2 /\ 2:r2 = 0" wouldn't be triggered on PPC.
I guess we will get the same behavior on ARM/ARM64, Will?
If a normal store could break chain, while a RmW atomic won't, do we want to call it out in the document and build our memory model around this?
I asked because in spin_unlock_wait() fix, we kind of relied on this. So it's good for us to clarify it?
Regards, Boqun
> } > > P2(int *x, int *y) > { > r1 = smp_load_acquire(y); > r2 = READ_ONCE(*x); > } > > Both ARM and powerpc allow the "after the dust settles" outcome (r1=2 && > r2=0), as does the current version of the early prototype Linux-kernel > memory model. > [unhandled content-type:application/pgp-signature] | |