Messages in this thread | | | Subject | Re: [PATCH net-next 6/7] net/faraday: Fix phy link irq on Aspeed G5 SoCs | From | Benjamin Herrenschmidt <> | Date | Tue, 20 Sep 2016 22:13:14 +1000 |
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On Tue, 2016-09-20 at 16:00 +0930, Joel Stanley wrote: > On Aspeed SoC with a direct PHY connection (non-NSCI), we receive > continual PHYSTS interrupts: > > [ 20.280000] ftgmac100 1e660000.ethernet eth0: [ISR] = 0x200: PHYSTS_CHG > [ 20.280000] ftgmac100 1e660000.ethernet eth0: [ISR] = 0x200: PHYSTS_CHG > [ 20.280000] ftgmac100 1e660000.ethernet eth0: [ISR] = 0x200: PHYSTS_CHG > [ 20.300000] ftgmac100 1e660000.ethernet eth0: [ISR] = 0x200: PHYSTS_CHG > > This is because the driver was enabling low-level sensitive interrupt > generation where the systems are wired for high-level. All CPU cycles > are spent servicing this interrupt.
If this is a system wiring issue, should it be represented by a DT property ?
Cheers, Ben.
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