| Subject | Re: [PATCH 4.4 017/192] [PATCH 017/135] clk: xgene: Fix divider with non-zero shift value | From | Ben Hutchings <> | Date | Tue, 20 Sep 2016 12:39:49 +0100 |
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On Mon, 2016-09-12 at 18:58 +0200, Greg Kroah-Hartman wrote: > 4.4-stable review patch. If anyone has any objections, please let me know. > > ------------------ > > [ Upstream commit 1382ea631ddddb634850a3795527db0feeff5aaf ] > > The X-Gene clock driver missed the divider shift operation when > set the divider value. > > Signed-off-by: Loc Ho <lho@apm.com> > Fixes: 308964caeebc ("clk: Add APM X-Gene SoC clock driver") > Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> > Signed-off-by: Sasha Levin <alexander.levin@verizon.com> > Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> > --- > drivers/clk/clk-xgene.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > --- a/drivers/clk/clk-xgene.c > +++ b/drivers/clk/clk-xgene.c > @@ -351,7 +351,8 @@ static int xgene_clk_set_rate(struct clk > /* Set new divider */ > data = xgene_clk_read(pclk->param.divider_reg + > pclk->param.reg_divider_offset); > - data &= ~((1 << pclk->param.reg_divider_width) - 1); > + data &= ~((1 << pclk->param.reg_divider_width) - 1) > + << pclk->param.reg_divider_shift; [...]
This still does the wrong thing when the shift value is non-zero: it clears all bits to the right of the divider field in data. I think the correct assignment is:
data &= ~(((1 << pclk->param.reg_divider_width) - 1) << pclk->param.reg_divider_shift);
Ben.
-- Ben Hutchings Software Developer, Codethink Ltd.
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