Messages in this thread | | | Subject | Re: [GIT PULL] Greybus driver subsystem for 4.9-rc1 | From | Bryan O'Donoghue <> | Date | Thu, 15 Sep 2016 11:47:13 +0100 |
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On Thu, 2016-09-15 at 11:35 +0100, Bryan O'Donoghue wrote: >
Here's a slightly better diagram.
PMIC -> refclk provided to each (timer) element below.
MSM8994(timer) -- > USB WD8a APBridgeA (timer) -> UniPro bus WD8a -> Module(timer) with UART WD1 -> Module(timer) with GPIO WD2 -> Module(timer) with blah WD3 -> SPI bus -> SVC(timer) Owns FrameTime GPIO {WD0...WDn}
So yes, each processor has it's own timer. We aren't trying to read the MSM's FrameTime.
--- bod
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