Messages in this thread Patch in this message | | | From | Harry Pan <> | Subject | [PATCH] perf/x86/rapl: Enable Baytrail/Braswell RAPL support | Date | Sun, 11 Sep 2016 11:18:54 +0800 |
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This patch enables RAPL counters (energy consumption counters) support for Intel Baytrail and Braswell processors (Model 55 and 76):
The Silvermont/Airmont microarchitecture actually uses fixed energy status unit (ESU) in smallest unit of microjoule, this patch adds quirk for these Atom processors (BYT/BSW) to calculate energy increment in 2^ESU microjoules.
ESU and power domains refer to Intel Software Developers' Manual, Vol. 3C, Order No. 325384, Table 35-8.
v2: simplify setting rapl_hw_unit[] to reduce runtime overhead.
Usage example:
$ perf list $ perf stat -a -e power/energy-cores/,power/energy-pkg/ sleep 10
This patch also enables multiple quirks.
Signed-off-by: Harry Pan <harry.pan@intel.com> --- arch/x86/events/intel/rapl.c | 49 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+)
diff --git a/arch/x86/events/intel/rapl.c b/arch/x86/events/intel/rapl.c index 94abfdb..2af6c18 100644 --- a/arch/x86/events/intel/rapl.c +++ b/arch/x86/events/intel/rapl.c @@ -110,6 +110,10 @@ static const char *const rapl_domain_names[NR_RAPL_DOMAINS] __initconst = { #define RAPL_IDX_KNL (1<<RAPL_IDX_PKG_NRG_STAT|\ 1<<RAPL_IDX_RAM_NRG_STAT) +/* Baytrail/Braswell clients have PP0, PKG */ +#define RAPL_IDX_BYT (1<<RAPL_IDX_PP0_NRG_STAT|\ + 1<<RAPL_IDX_PKG_NRG_STAT) + /* * event code: LSB 8 bits, passed in attr->config * any other bit is reserved @@ -458,6 +462,14 @@ RAPL_EVENT_ATTR_STR(energy-ram.scale, rapl_ram_scale, "2.3283064365386962890 RAPL_EVENT_ATTR_STR(energy-gpu.scale, rapl_gpu_scale, "2.3283064365386962890625e-10"); RAPL_EVENT_ATTR_STR(energy-psys.scale, rapl_psys_scale, "2.3283064365386962890625e-10"); +/* + * Some Atom series processors (BYT/BSW) have fixed + * energy status unit (ESU) in smallest unit of microjoule, + * and its increment is in 2^ESU microjoules. + */ +RAPL_EVENT_ATTR_STR(energy-cores.scale, rapl_byt_cores_scale, "1.0e-6"); +RAPL_EVENT_ATTR_STR(energy-pkg.scale, rapl_byt_pkg_scale, "1.0e-6"); + static struct attribute *rapl_events_srv_attr[] = { EVENT_PTR(rapl_cores), EVENT_PTR(rapl_pkg), @@ -539,6 +551,18 @@ static struct attribute *rapl_events_knl_attr[] = { NULL, }; +static struct attribute *rapl_events_byt_attr[] = { + EVENT_PTR(rapl_cores), + EVENT_PTR(rapl_pkg), + + EVENT_PTR(rapl_cores_unit), + EVENT_PTR(rapl_pkg_unit), + + EVENT_PTR(rapl_byt_cores_scale), + EVENT_PTR(rapl_byt_pkg_scale), + NULL, +}; + static struct attribute_group rapl_pmu_events_group = { .name = "events", .attrs = NULL, /* patched at runtime */ @@ -634,6 +658,23 @@ static void rapl_hsx_quirk(void) rapl_hw_unit[RAPL_IDX_RAM_NRG_STAT] = 16; } +static void rapl_byt_quirk(void) +{ + int i; + + /* + * Some Atom processors (BYT/BSW) have 2^ESU microjoules + * increment, refer to Software Developers' Manual, Vol. 3C, + * Order No. 325384, Table 35-8 of MSR_RAPL_POWER_UNIT. + * + * TODO: In order to fit BYT/BSW quirk model, here remind + * this generates timer rate in 80ms; by default + * ESU of BYT/BSW is 5, so it leads (1000/200)*2^4. + */ + for (i = 0; i < NR_RAPL_DOMAINS; i++) + rapl_hw_unit[i] = 32 - rapl_hw_unit[i]; +} + static int rapl_check_hw_unit(const struct intel_rapl_model_desc *model) { u64 msr_rapl_power_unit_bits; @@ -745,6 +786,12 @@ static const struct intel_rapl_model_desc skl_rapl_init __initconst = { .attrs = rapl_events_skl_attr, }; +static const struct intel_rapl_model_desc byt_rapl_init __initconst = { + .quirk = rapl_byt_quirk, + .cntr_mask = RAPL_IDX_BYT, + .attrs = rapl_events_byt_attr, +}; + static const struct x86_cpu_id rapl_cpu_match[] __initconst = { X86_RAPL_MODEL_MATCH(INTEL_FAM6_SANDYBRIDGE, snb_rapl_init), X86_RAPL_MODEL_MATCH(INTEL_FAM6_SANDYBRIDGE_X, snbep_rapl_init), @@ -768,6 +815,8 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = { X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_DESKTOP, skl_rapl_init), X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_X, hsx_rapl_init), + X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_SILVERMONT1, byt_rapl_init), + X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_AIRMONT, byt_rapl_init), X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init), {}, }; -- 2.6.6
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