Messages in this thread | | | Date | Wed, 3 Aug 2016 08:44:43 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH 1/1] EDAC, sb_edac: Fix channel reporting on Knights Landing |
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On Sat, Jul 23, 2016 at 01:44:49AM +0200, Lukasz Odzioba wrote: > On Intel Xeon Phi Knights Landing processor family the channels > of memory controller have untypical arrangement - MC0 is mapped to > CH3,4,5 and MC1 is mapped to CH0,1,2. This causes EDAC driver to > report the channel name incorrectly. > > We missed this change earlier, so the code already contains > similar comment, but the translation function is incorrect. > > Without this patch: > errors in DIMM_A and DIMM_D were reported in DIMM_D > errors in DIMM_B and DIMM_E were reported in DIMM_E > errors in DIMM_C and DIMM_F were reported in DIMM_F > > Fixes: d0cdf9003140 ("sb_edac: Add Knights Landing (Xeon Phi gen 2) support") > Signed-off-by: Lukasz Odzioba <lukasz.odzioba@intel.com> > Signed-off-by: Hubert Chrzaniuk <hubert.chrzaniuk@intel.com>
What is that SOB supposed to mean?
-- Regards/Gruss, Boris.
ECO tip #101: Trim your mails when you reply. --
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