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    SubjectRE: [PATCH v2 00/13] sched: Clean-ups and asymmetric cpu capacity support
    Date
    Hi,

    I tested these patches on Renesas SoC r8a7790(CA15*4 + CA7*4)
    and your preview branch[1] on Renesas SoC r8a7795(CA57*4 + CA53*4).

    > Test 0:
    > for i in `seq 1 10`; \
    > do sysbench --test=cpu --max-time=3 --num-threads=1 run;
    > \
    > done \
    > | awk '{if ($4=="events:") {print $5; sum +=$5; runs +=1}} \
    > END {print "Average events: " sum/runs}'
    >
    > Target: ARM TC2 (2xA15+3xA7)
    >
    > (Higher is better)
    > tip: Average events: 146.9
    > patch: Average events: 217.9
    >
    Target: Renesas SoC r8a7790(CA15*4 + CA7*4)
    w/ capacity patches: Average events: 200.2
    w/o capacity patches: Average events: 144.4

    Target: Renesas SoC r8a7795(CA57*4 + CA53*4)
    w/ capacity patches : 3587.7
    w/o capacity patches : 2327.8

    > Test 1:
    > perf stat --null --repeat 10 -- \
    > perf bench sched messaging -g 50 -l 5000
    >
    > Target: Intel IVB-EP (2*10*2)
    >
    > tip: 4.861970420 seconds time elapsed ( +- 1.39% )
    > patch: 4.886204224 seconds time elapsed ( +- 0.75% )
    >
    > Target: ARM TC2 A7-only (3xA7) (-l 1000)
    >
    > tip: 61.485682596 seconds time elapsed ( +- 0.07% )
    > patch: 62.667950130 seconds time elapsed ( +- 0.36% )
    >
    Target: Renesas SoC r8a7790(CA15*4) (-l 1000)
    w/ capacity patches: 38.955532040 seconds time elapsed ( +- 0.12% )
    w/o capacity patches: 39.424945580 seconds time elapsed ( +- 0.10% )

    Target: Renesas SoC r8a7795(CA57*4) (-l 1000)
    w/ capacity patches : 29.804292200 seconds time elapsed ( +- 0.37% )
    w/o capacity patches : 29.838826790 seconds time elapsed ( +- 0.40% )

    Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com>

    [1] git://linux-arm.org/linux-power.git capacity_awareness_v2_arm64_v1

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